研究目的
To improve the phase noise significantly in 1/f 3 region for an oscillator employing film bulk acoustic resonator (FBAR) by adopting a class-C architecture.
研究成果
The class-C FBAR oscillator demonstrates significant phase noise improvement, with a 17 dBc/Hz enhancement at 100 kHz offset from a 1.9 GHz carrier compared to previous designs. The optimized design achieves a figure of merit of 227, indicating superior performance.
研究不足
The study focuses on phase noise improvement in the 1/f 3 region and may not address all aspects of oscillator performance. The adaptive biasing circuit adds complexity to the design.
1：Experimental Design and Method Selection:
The study employs a class-C architecture for an FBAR oscillator to reduce noise from the current-source transistor in a cross-coupled topology. An adaptive biasing circuit ensures oscillation start-up.
2：Sample Selection and Data Sources:
The design is implemented in 0.18 μm CMOS technology, with FBAR represented by a modified Butterworth Van Dyke (MBVD) model.
3：18 μm CMOS technology, with FBAR represented by a modified Butterworth Van Dyke (MBVD) model.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: The oscillator is designed with specific capacitors (Ctail and Cs) to optimize phase noise performance.
4：Experimental Procedures and Operational Workflow:
The design includes post-layout simulation incorporating all parasitic elements to evaluate phase noise improvement.
5：Data Analysis Methods:
Phase noise performance is compared with previous designs to quantify improvements.
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