研究目的
To model the experimentally observed innate stochasticity in memristors in a circuit compatible format and explore its implications for neuromorphic engineering circuits design and digital designs based on nondeterministic memristor logic.
研究成果
The paper presents a circuit simulator compatible model for stochasticity in memristors, verified through distribution fitting and simulation. It highlights the model's potential in neuromorphic applications and cautions its use in digital designs due to inherent variability.
研究不足
The model's applicability is limited to threshold-based memristor models. Digital applications may require stringent settings to avoid functionality issues due to stochastic behavior.