研究目的
Demonstrating in-plane InAs/Si TFETs monolithically integrated on Si, using template-assisted selective epitaxy approach, and analyzing factors limiting device performance.
研究成果
The paper presents InAs/Si TFETs that are monolithically integrated on Si using a scalable and CMOS-compatible process. The devices show state-of-the-art performance but are limited by heterojunction defects. Future work needs to focus on reducing defect concentrations to achieve sub-60 mV/decade operation.
研究不足
The performance of the TFETs is limited by defects, particularly at the heterojunction, which affects the subthreshold swing and ON-current.
1：Experimental Design and Method Selection:
The study employs a template-assisted selective epitaxy approach for the fabrication of InAs/Si TFETs.
2：Sample Selection and Data Sources:
The devices are fabricated on a conventional silicon-on-insulator (SOI) substrate.
3：List of Experimental Equipment and Materials:
Includes e-beam lithography, metal-organic chemical vapor deposition, and various etching processes.
4：Experimental Procedures and Operational Workflow:
Detailed steps involve defining the p+-Si drain, fabricating the template, growing InAs source, depositing gate-stack, and creating source and drain contacts.
5：Data Analysis Methods:
Electrical characterization and low-temperature measurements are used to analyze device performance.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
