研究目的
Investigating the development of a low-power low-jitter all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of a traditional time-to-digital converter (TDC).
研究成果
The proposed ADC-based AD-PLL (ADC-PLL) using voltage-domain digitization in sub-sampling architecture achieves high resolution in phase digitalization, leading to low in-band phase noise in an AD-PLL. The experimental results demonstrate an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz, with a power consumption of only 4.2 mW.
研究不足
The performance of analog PLLs tends to be limited by device leakage and low supply voltages in highly scaled CMOS technology, causing degradation in integrated phase noise and spur performance.
