研究目的
To demonstrate a sub-0.5 electron read noise VGA CMOS image sensor integrated in a standard CMOS process through circuit optimization without any process refinements.
研究成果
The work demonstrates that deep sub-electron noise can be achieved in a full VGA APS using a standard CIS process through proper circuit noise optimization. The proposed techniques result in pixels featuring an input-referred TRN as low as 0.25 e? rms, with the majority peaking at 0.48 e? rms. The approach does not compromise dynamic range, lag, or PRNU, and the QE of the PPD is not affected by the neighboring PMOS n-wells.
研究不足
The study is limited to room temperature characterization and does not explore the sensor's performance under varying environmental conditions. The use of a standard CMOS process without refinements may limit further noise reduction.
