研究目的
To develop a multi-level evolutionary approach to realize complex computational circuits called Embedded-Cascaded Hierarchically Evolved Logic Output Networks (ECHELON) for mixed-signal system-on-chip (SoC) devices, addressing challenges of hardware-software co-design optimization, device signal range constraints, and limited precision.
研究成果
ECHELON is developed as a multi-level embedded strategy to evolve transcendental functions as a truncated fractional power series of the independent variable, achieving significant speedup in performance and reducing error in the final mathematical approximation. The approach decouples mathematical complexity from computation running time and is promising for computation and analysis of complex datasets.
研究不足
The approach is constrained by the device ADC range of 0-4.08V and the need to prevent overflow in subsequent computations. The accuracy of the evolved circuits is applicable only within the device range for which evolution was performed.
1：Experimental Design and Method Selection:
The ECHELON technique utilizes analog evolved building blocks and refines their output using digital fabric to compose power series expansions of transcendental functions on a field-programmable SoC (PSoC).
2：Sample Selection and Data Sources:
The independent variable x is incremented in steps of 0.016V over a range of 0-4.08V, with 256 data points.
3：016V over a range of 0-08V, with 256 data points.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: Cypress PSoC-5LP mixed-signal SoC.
4：Experimental Procedures and Operational Workflow:
Analog evolution is performed to obtain a rough approximation, followed by scaled analog evolution to handle outputs beyond device limit, and then Differential Digital Correction (DDC) to refine the output.
5：Data Analysis Methods:
The Total Error is calculated as the summation of absolute error of the computed output over the operating range.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
