研究目的

Investigating the potential of vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates for advanced sub-5nm technology nodes, in comparison to finFETs, and their application in highly dense memory cells such as SRAMs and as selector devices for ultra-scaled MRAMs.

研究成果

Vertically stacked lateral NS GAA FETs are expected to outperform finFETs and deliver a better power-performance metric for logic applications for advanced sub-5nm nodes. Vertical NW or NS FETs have the potential to enable denser and more energy efficient SRAMs or MRAMs. A cost-effective co-integration scheme to obtain high-performance logic with increased on-chip memory is feasible.

研究不足

The study acknowledges the need for further optimizations of the device architecture to maintain scaling gains and the challenges in integrating these novel transistor architectures with existing technologies.