研究目的
To improve energy efficiency and performance of combinatorial circuits by manipulating their critical and noncritical paths using Dual Mode Logic (DML) gates.
研究成果
The proposed DML approach significantly improves both the performance and energy efficiency of combinatorial circuits. At VDD = 400 mV, performance improvement of X2 and energy consumption reduction of X2.5 are achieved. At VDD = 1.1 V, improvements of 1.3X in performance and 1.5X in energy are observed.
研究不足
The study is limited to a 128 bit carry skip adder as a benchmark. The approach's scalability and applicability to other combinatorial circuits and different technologies are not extensively explored.
1：Experimental Design and Method Selection:
The study utilizes DML gates to manipulate critical and noncritical paths in combinatorial circuits for energy efficiency and performance improvement.
2：Sample Selection and Data Sources:
A 128 bit carry skip adder is used as a benchmark to evaluate the proposed approach.
3：List of Experimental Equipment and Materials:
Simulations are carried out in a standard 40 nm digital CMOS process with VDD = 400 mV and VDD =
4：1 V. Experimental Procedures and Operational Workflow:
The approach involves locating the design’s critical paths and operating these paths in the boosted performance mode, while noncritical paths are operated in the low energy DML mode.
5：Data Analysis Methods:
Performance and energy consumption improvements are measured and compared with a standard CMOS implementation.
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