研究目的
To develop a compact silicon-photonic receiver integrated with a 28-nm CMOS transimpedance-amplifier (TIA) chip for high-speed and high-efficiency operation, suitable for practical use at high temperatures.
研究成果
The developed silicon-photonic receiver demonstrates error-free operation at 25 Gb/s across a range of temperatures, with competitive sensitivity and power consumption metrics. The photonics—electronics convergence design technique proves effective for practical applications, including high-temperature environments.
研究不足
The study acknowledges the influence of the low-resistivity SOI wafer on CPW performance and the need for further optimization to reduce deterministic jitters caused by LC resonance in power lines.
1：Experimental Design and Method Selection:
The receiver was designed using a photonics—electronics convergence design technique, focusing on the interfaces between optical and electrical components. Optical pins were used for alignment, and an aluminum stripline was employed to enhance bandwidth.
2：Sample Selection and Data Sources:
The study utilized a silicon-on-insulator (SOI) wafer with integrated germanium photodetectors (Ge-PDs) and a CMOS-TIA chip.
3：List of Experimental Equipment and Materials:
Equipment included a LiNbO3 Mach–Zehnder modulator, tunable laser source, and sampling oscilloscope. Materials included UV-curable resin for optical pins and aluminum for striplines.
4：Experimental Procedures and Operational Workflow:
Optical signals were generated and input into the receiver, with performance evaluated through eye-diagram measurements and bit error rate (BER) tests at varying temperatures.
5：Data Analysis Methods:
Data was analyzed for transimpedance gain, bandwidth, and power consumption, with performance metrics compared at 25 and 85 °C.
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