研究目的
To propose a discrete-time IIR low-pass ?lter that achieves a high-order of ?ltering through a charge-sharing rotation and to multiply its sampling rate through pipelining.
研究成果
The proposed high-order discrete-time charge rotating IIR filter structure is experimentally verified, showing state-of-the-art performance including very low power consumption, the lowest input-referred noise, very wide tuning range, and excellent linearity.
研究不足
The filter's performance is subject to the limitations of the TSMC 65 nm CMOS technology and the design choices made for the gm-cell and capacitors.
1：Experimental Design and Method Selection:
The filter is designed to operate in either a voltage-sampling or charge-sampling mode, using switches, capacitors, and a simple gm-cell.
2：Sample Selection and Data Sources:
The filter prototype is implemented in TSMC 65 nm CMOS.
3：List of Experimental Equipment and Materials:
The filter uses switches, capacitors, a simple gm-cell, and is implemented in TSMC 65 nm CMOS.
4：Experimental Procedures and Operational Workflow:
The filter's sampling rate is multiplied through pipelining, and it can operate in two modes with programmable bandwidth.
5：Data Analysis Methods:
The filter's performance is evaluated in terms of bandwidth, stop-band rejection, linearity, noise, and power consumption.
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