研究目的
Investigating the design and implementation of a variable-rate FEC decoder architecture for high-throughput optical communication systems to adapt to varying channel conditions.
研究成果
The introduced VLSI architecture for high-throughput variable-rate FEC decoders based on product codes demonstrates viability for flexible, energy-efficient decoders in high-throughput systems. The implementation achieves a net coding gain range from 9.96 to 10.38 dB, with throughputs exceeding 400 Gbps and decoding latencies below 53 ns, showing limited circuit overhead for handling different modes.
研究不足
The coding gain range is limited by the overhead of the component codes and the constraint of achieving throughputs in excess of 400 Gbps. Longer component codes or higher error-correction capability could extend the range but at the cost of increased complexity and power dissipation.
1：Experimental Design and Method Selection:
The study introduces a variable-rate FEC decoder architecture based on product codes, utilizing BCH component codes for error correction. The architecture supports multiple modes by varying code overhead and decoding iterations.
2：Sample Selection and Data Sources:
The research uses simulated data for functional verification, employing uniformly-distributed data and random bit flips to simulate channel conditions.
3：List of Experimental Equipment and Materials:
The decoder was implemented using VHDL and synthesized in a 28-nm process technology. Simulation and synthesis tools include Cadence Incisive and Cadence Genus.
4：Experimental Procedures and Operational Workflow:
The decoder's performance was evaluated through simulation and synthesis, measuring net coding gain, throughput, latency, and power dissipation.
5：Data Analysis Methods:
The study employs BER analysis and net coding gain evaluation at a post-FEC BER of 10?15, using MATLAB for data extrapolation.
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