摘要： Reducing the capacitance of programmable capacitor arrays (PCAs), commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data are available for small capacitors. We report mismatch measurement for a 2-fF poly–insulator–poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors’ knowledge. Instead of using complicated custom on-chip circuitry, direct mismatch measurement is demonstrated and veri?ed using Monte Carlo simulations and experimental measurements. Capacitive test structures composed of 9-bit PCAs are implemented in a low-cost 0.35-μm CMOS process. Measured data are compared to the mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2-fF unit capacitor, which is better than the reported mismatch of metal–oxide–metal (MOM) fringing capacitors implemented in an advanced 32-nm CMOS process.