1：Experimental Design and Method Selection:

The study focuses on the transconductance efficiency and amplification characteristics of DSFETs used in analog ICs. The methodology involves fabricating and measuring individual CNT-based DSFETs and comparing their performance with normal CNT FETs.

2：Sample Selection and Data Sources:

n-Doped graphene was grown on a copper substrate and transferred to silicon wafers covered by 300 nm thick SiO2. CNT arrays were transferred onto the same Si/SiO2 substrate with graphene electrodes.

3：CNT arrays were transferred onto the same Si/SiO2 substrate with graphene electrodes. List of Experimental Equipment and Materials:

3. List of Experimental Equipment and Materials: Electron beam lithography (EBL), O2 reactive ion etching (RIE), electron beam evaporation (EBE), atomic layer deposition (ALD), and scanning electron microscope (SEM) were used for fabrication and characterization.

4：Experimental Procedures and Operational Workflow:

The fabrication process involved patterning graphene as the source of DSFETs, transferring CNT arrays, forming Pd drain electrodes, depositing and oxidizing yttrium to form yttrium oxide film, and patterning Pd gate electrodes.

5：Data Analysis Methods:

The transconductance efficiency (gm/Ids) and peak transconductance (gmax) were measured and compared between DSFETs and normal CNT FETs. An analytic model based on the Landauer–Datta–Lundstrom transport theory was used to understand the transport mechanism.