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[IEEE 2018 19th International Conference on Electronic Packaging Technology (ICEPT) - Shanghai (2018.8.8-2018.8.11)] 2018 19th International Conference on Electronic Packaging Technology (ICEPT) - Research on Thermal Analysis of Iris Recognition Module Package Structure

DOI:10.1109/ICEPT.2018.8480569 出版年份:2018 更新时间:2025-09-23 15:21:01
摘要: The existing iris recognition module is realized by assembly, which has large volume, high power consumption. The iris recognition module does not conform to the light and thin development trend of integrated circuits. Therefore, the industry is considering building a new iris recognition module from the bare chip and micro interconnect technology. The new module integrates a number of bare chips and passive devices in a limited space, and its thermal performance becomes more complex. It performance systematically. In this paper, thermal performance of the iris recognition module is systematically studied by the finite element method, and the influence of the thermal power of the chip, the thermal conductivity of the material and the area of PCB on the temperature and thermal resistance of the package are discussed. The results show that the thermal conductivity of chip material, the thermal power consumption of chip and the area of PCB have significant influence on packaging junction and thermal resistance of package. Package junction temperature and thermal resistance first decrease rapidly with the heat transfer coefficient of the package material, and then gradually tends to be horizontal, The effect of PCB area on the thermal performance of packaging is similar to that of the loading material, and the thermal dissipation power of the package is linearly increasing with the junction temperature of the package, and it has a horizontal linear relationship with the thermal resistance of the package.
作者: Lei Wang,Zhangping Yang,Xiyou Wang,Daoguo Yang,Miao Cai
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To study the thermal performance of a new iris recognition module designed with bare chip and microinterconnection technology, focusing on the influence of chip thermal power, material thermal conductivity, and PCB area on package temperature and thermal resistance.

The thermal conductivity of the chip material, the thermal power consumption of the chip, and the area of the PCB significantly influence the package junction temperature and thermal resistance. The choice of packaging material is critical for thermal management, with the thermal resistance of the package mainly determined by the packaging material and structure. The heat dissipation power of the package is linearly related to the junction temperature and has a horizontal linear relationship with the thermal resistance.

The study ignores the influence of heat radiation and gold wire in the simulation, focusing solely on heat conduction and surface effects. The practical application may require consideration of these factors for comprehensive thermal management.

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