研究目的
To develop and implement a computational methodology for reconstructing events with a large number of charged-particle tracks in pixel and silicon strip detectors at 40 MHz, matching the LHC requirements.
研究成果
The prototype demonstrates the feasibility of fast track-finding with an FPGA-based system at MHz rates. The design can be scaled for larger detectors and higher input rates, with potential applications in providing reconstruction primitives to the high-level trigger in parallel with raw detector information.
研究不足
The prototype's scalability to larger area detectors and higher input rates needs further testing. The momentum resolution was found to be 25% broader for the retina algorithm compared to offline algorithms.
1：Experimental Design and Method Selection:
The study employs a parallel pattern-recognition algorithm inspired by the early stages of image processing by the brain, implemented in FPGAs.
2：Sample Selection and Data Sources:
The prototype uses the detailed geometry and charged-particle activity of a large tracking detector currently in operation.
3：List of Experimental Equipment and Materials:
The prototype is based on readout boards equipped with Altera Stratix III FPGAs.
4：Experimental Procedures and Operational Workflow:
The algorithm processes hits from detector layers, accumulates weights for track hypotheses, and identifies tracks as local maxima in the parameter space.
5：Data Analysis Methods:
The performance is assessed based on track-finding efficiency, fake track rate, and momentum resolution.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
