研究目的
To demonstrate the low-temperature epitaxial growth of BeO on 4H silicon carbide (4H-SiC) (0 0 1) via ALD for the ?rst time and evaluate its suitability as a gate dielectric material in SiC-based metal-oxide-semiconductor-?eld-e?ect-transistors (MOSFETs).
研究成果
The study successfully demonstrated the low-temperature epitaxial growth of high-quality BeO on 4H-SiC using ALD, with excellent material properties suitable for power transistors. The BeO film exhibited high crystallinity, thermal stability, and low interface trap density, making it a promising candidate for gate dielectric applications in SiC-based MOSFETs.
研究不足
The study demonstrates the potential of ALD BeO as a gate dielectric for SiC power devices but does not explore the long-term stability or performance under high electric fields and temperatures typical in power electronics applications. The formation of a small amount of SiO2 interfacial oxide after high-temperature annealing could affect the interface properties.
1：Experimental Design and Method Selection:
The study utilized atomic layer deposition (ALD) for the epitaxial growth of BeO on 4H-SiC at a low temperature of 250 °C. The growth mechanism and crystallinity were analyzed using domain-matching epitaxy (DME) to accommodate the large lattice mismatch between BeO and SiC.
2：Sample Selection and Data Sources:
4H-SiC (0 0 1) substrates were used for the epitaxial growth of BeO. The substrates were cleaned with an aqueous solution of HF: DI water = 10: 1 before deposition.
3：List of Experimental Equipment and Materials:
ALD was performed using an Atomic Classic ALD instrument with DMBe as the precursor. Characterization techniques included TEM (JEOL JEM-ARM 200F), XPS (Thermo Fisher Scienti?c K-ALPHA), XRD (Rigaku SmartLab), Raman spectroscopy (Horiba-Lab Ram ARAMIS), and C-V measurements (Keysight B1505A).
4：Experimental Procedures and Operational Workflow:
The BeO deposition involved 200 cycles at
5：8 ?/cycle with specific pulse and purge times. Post-deposition annealing was performed at 600 °C in ambient NMOS capacitors were fabricated with Mo top electrodes and Ni backside ohmic contacts. Data Analysis Methods:
The crystallinity and epitaxial relationship were analyzed using TEM, SAD, and XRD. The thermal stability and interface composition were evaluated using XPS and Raman spectroscopy. Electrical properties were assessed through C-V measurements and the Terman method for interface trap density calculation.
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