研究目的
To expand the software-defined region of optical line terminals (OLTs) by focusing on implementing PHY-layer processes in software, specifically burst-frame synchronization for flexible access systems.
研究成果
The proposed burst-frame synchronization algorithm using array-access bitshift and dual-stage detection significantly reduces computational complexity, enabling 10-Gbps real-time processing on general-purpose hardware. The feasibility test for 10G-EPON application confirms the algorithm's performance, with processing speeds about 10,500 times faster than conventional methods and minimal penalty in BER performance when combined with FEC. Future work aims to softwarize the complete PCS layer of OLT and improve system scalability for commercialization.
研究不足
The power consumption of the processors utilized in the test is about 540 W per PON-port, which is higher than that of hardware-implemented OLTs (about 20 W per PON-port). This poses a challenge for commercial deployment despite the advancements in reducing power consumption through dynamic frequency and voltage optimization, power gating, and semiconductor process shrinking.
1：Experimental Design and Method Selection:
The study focuses on implementing burst-frame synchronization in software using GPUs for high computational efficiency. The methodology includes a novel bitshift implementation using array access and a dual-stage detection algorithm to reduce computational complexity.
2：Sample Selection and Data Sources:
The experiment uses 10G-EPON frames standardized in IEEE
3：3av, with parameters set to NSP = 66 bit, NBD = 66 bit, and 130 KByte payload length. The idle signal and payload are generated from a 223 (cid:
80) 1 pseudo-random bit sequence (PRBS).
4：List of Experimental Equipment and Materials:
The server configuration includes two 2.20 GHz CPUs (Intel Broadwell Xeon E5-2699v4), a GPU (NVIDIA Tesla P100), and an IF circuit (TB-7VX-690T-PCIEXP). Optical modules are connected via SFP+ modules.
5：20 GHz CPUs (Intel Broadwell Xeon E5-2699v4), a GPU (NVIDIA Tesla P100), and an IF circuit (TB-7VX-690T-PCIEXP). Optical modules are connected via SFP+ modules.
Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: The setup assumes PON upstream transmission, with a DML generating a 10.3125-Gbps optical signal. The optical power is adjusted by a VOA, and PPG generates repeated signals as PON frames with idle signals inserted between them.
6：3125-Gbps optical signal. The optical power is adjusted by a VOA, and PPG generates repeated signals as PON frames with idle signals inserted between them.
Data Analysis Methods:
5. Data Analysis Methods: The performance is evaluated based on processing time and frame detection error rate (FDER), with theoretical and simulated results compared to real-time measurements.
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