研究目的
To solve the leakage current saturation of Topmetal-???? ? and to maintain its low noise by designing Topmetal-??????, and to study the optimization of parameters for induction efficiency.
研究成果
The structure of Section C in Topmetal-?????? chip, where the electrode is covered by an insulating layer and the guard ring is exposed, is capable of solving the leakage current saturation problem while maintaining the ability to receive induced signals. Simulations indicate that thinner epoxy resin thickness and larger electrode size contribute to higher induction efficiency, suggesting that the structure of Section C is preferred for designing a pixelated CdZnTe detector to achieve high spatial resolution.
研究不足
The study is limited by the thickness of the epoxy glue used to connect the chip and CdZnTe crystal, which cannot be negligible and affects the induction efficiency. Additionally, the charge diffusion and repulsion affect the charge distribution, which could be optimized further.
1：Experimental Design and Method Selection:
The study involves designing a new chip, Topmetal-??????, with three different sections to address leakage current saturation and maintain low noise. The methodology includes testing the chip's performance when coupled with a CdZnTe detector and simulating the charge induction efficiency under different parameters.
2：Sample Selection and Data Sources:
A CdZnTe crystal is used as the sensitive layer coupled with the Topmetal-?????? chip. The data sources include experimental results from testing the chip's sections under various bias voltages and simulation results from finite element method (FEM) simulations.
3：List of Experimental Equipment and Materials:
The equipment includes a Topmetal-?????? chip, CdZnTe crystal, epoxy resin adhesive, pulse laser, and Printed Circuit Board (PCB).
4：Experimental Procedures and Operational Workflow:
The procedure involves coupling the CdZnTe crystal with the Topmetal-?????? chip using epoxy resin adhesive, applying different bias voltages, and testing the chip's performance. The operational workflow includes measuring the percentage of saturated pixels versus bias voltage and testing induced signals with a pulse laser.
5：Data Analysis Methods:
The analysis involves comparing the performance of the three sections of the chip under different conditions and simulating the charge induction efficiency using FEM based on COMSOL.
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