1：Experimental Design and Method Selection:

The TFTs were fabricated using RF magnetron sputtering with a dual-active-layer structure of IZO:Li/ZTO:Li. The influence of ZTO:Li layer thickness on the electrical characteristics and bias-stress stability was investigated.

2：Sample Selection and Data Sources:

The samples were prepared on heavily doped p-type Si substrates with a 250-nm SiO2 layer as the gate insulator.

3：List of Experimental Equipment and Materials:

RF magnetron sputtering system, UV–vis spectrophotometer, X-ray diffractometer (XRD), surface profiler, and Keithley 4200-SCS for electrical characterization.

4：Experimental Procedures and Operational Workflow:

The IZO:Li and ZTO:Li layers were deposited sequentially, followed by annealing at 400 °C in O2 for 30 min. Al source/drain electrodes were deposited by thermal evaporation.

5：Data Analysis Methods:

Electrical characteristics were analyzed using the saturation mobility (μSAT), threshold voltage (VTH), sub-threshold swing (SS), and current on/off ratio (ION/IOFF).