研究目的
Investigating the effect of the use of a supersonic-soldering method on the solder layers between Si chips and sapphire substrates for programmable Josephson voltage standard (PJVS) chips.
研究成果
The void ratio in the solder layers formed with a supersonic-soldering method was estimated to be approximately 20 % to 40 %, which is much improved compared to that obtained with a conventional soldering method. The study suggests the improvement of the thermal contact between the PJVS chips and the sapphire substrates by using the supersonic-soldering method.
研究不足
The study mentions the presence of unintended voids in the InSn solder layer, which might affect the heat transfer between the PJVS chips and the sapphire substrates. The influence of these soldering methods on the thermal contact of PJVS chips is still under investigation.
1：Experimental Design and Method Selection:
The study used a scanning acoustic microscope to observe the InSn solder layers formed with a supersonic-soldering method between Si chips and sapphire substrates.
2：Sample Selection and Data Sources:
Four samples of Si chips bonded with InSn solder on sapphire (or Cu) substrates were prepared under different conditions.
3：List of Experimental Equipment and Materials:
Scanning acoustic microscope, InSn solder, Si chips, sapphire substrates, Cu substrates, Au buffer layers.
4：Experimental Procedures and Operational Workflow:
The samples were bonded with the supersonic-soldering method without flux in different conditions and observed using a scanning acoustic microscope.
5：Data Analysis Methods:
The void ratio in the solder layers was estimated based on the contrast of the microphotographs obtained from the scanning acoustic microscope.
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