研究目的
Investigating the asymmetric effects of gate-bias stress voltage on the stability under positive and negative gate-bias stress of a-IGZO TFTs.
研究成果
The study demonstrates asymmetric effects of gate-bias stress voltage on the stability of a-IGZO TFTs under PBS and NBS. The ?Vth increases with the increased VStress under PBS due to enhanced electron trapping, while it is nearly unaffected by VStress under NBS due to the insensitivity of electron-detrapping rate to the negative gate-bias voltage. N2O plasma back-channel treatment effectively improves the stability under NBS by reducing the density of oxygen-vacancy related donor-like states, with an optimal treatment time of 60s.
研究不足
The study does not explore the effects of other plasma treatments or alternative materials for improving the stability of a-IGZO TFTs under NBS. Additionally, the optimal N2O plasma treatment time (60s) may vary with different device configurations or fabrication processes.
1：Experimental Design and Method Selection:
The study investigates the effects of gate-bias stress voltage on the stability of a-IGZO TFTs under PBS and NBS. The methodology includes measuring the threshold voltage shift (?Vth) under different stress voltages and analyzing the effects of N2O plasma back-channel treatment.
2：Sample Selection and Data Sources:
Passivation-free bottom-gate staggered a-IGZO TFTs were fabricated on glass substrates.
3：List of Experimental Equipment and Materials:
A 150nm molybdenum (Mo) film for gate electrode, a 200nm SiO2 gate insulator (GI) by PECVD, a 50nm a-IGZO film by DC sputtering, and a 150nm Mo film for source/drain electrodes.
4：Experimental Procedures and Operational Workflow:
The devices were annealed at 250°C in O2 for 1 hour, followed by N2O plasma back-channel treatment at 150°C for different treatment times, and then annealed at 250°C for 20 minutes. Device performance and stability under gate bias stress were measured in a dark environment by a Keithley 4200 semiconductor parameter analyzer in vacuum ambient.
5：Data Analysis Methods:
The threshold voltage shift (?Vth) was extracted from the transfer characteristics curves (Id-Vg) measured before and after the gate-bias stress.
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