摘要： Due to the approaching physical limits for further shrinking and scaling, an alternative way to keep the pace for performance increases of future complementary metal-oxide semiconductor (CMOS) devices is the introduction of high mobility channel materials. The implementation of these alternative materials is targeted for the technology nodes from 10 nm onward. In order to achieve low power and high performance logic devices, the scaling supply voltage (Vdd) has to be optimized. This can be achieved by using materials that have a very high mobility such as Ge (for p-type metal-oxide semiconductors (pMOS)) and IIIeV (for n-type metal-oxide semiconductors (nMOS)) (Skotnicki and Boeuf, 2010). For the fabrication of working devices, gate leakage through the buffer layer needs to be minimized, for example, through doping the buffer layer or by removing the leakage path altogether in a gate-all-around approach. Mobility can be maximized, for example, by deliberate material doping as well as by adjusting the strain and defectivity of the channel layer. The most promising material candidates are Ge for pMOS devices and InGaAs for nMOS devices. The reason for this is the high hole mobility of Ge and the high electron mobility of InGaAs. The hole mobility of a bulk Ge layer is approximately four times and the electron mobility of a bulk InGaAs layer is approximately six times higher when compared to the mobilities of a bulk Si layer. High performance for Ge-based pMOS devices has been demonstrated on a Si platform (Mitard et al., 2009). But in current CMOS devices the Si layer takes advantage of straining methods, which results in higher mobilities; so for the implementation of Ge the application of strain needs also to be considered. However, for InGaAs nMOS devices strain does not improve performance, which could be viewed as an advantage because straining devices becomes harder with more scaling.