摘要： An N -element array with receivers subject to an N -point spatial FFT leads to N directionally-orthogonal RF beams. FFTs are fast algorithms for computing an N -point DFT at reduced complexity. The brute-force computation of a DFT requires O(N 2) multiplications while an FFT provides the same computation at O(N log N ) multiplications. The digital chip area and power consumption of the DFT computation are still dominated by the multipliers required by the FFT used. In this paper, an approximation to the 16-point DFT is proposed which maintains mathematical properties close to the ideal 16-point DFT to obtain 16 RF beams by computing an approximate spatial DFT in every clock cycle at significantly lower area and power in the digital realization. The proposed approximation can be implemented using FFT-like fast algorithms that are multiplierless, thereby further reducing the digital chip area and power consumption associated with multiplication in a conventional FFT approach, to zero. A 16-beam beamformer employing a 16-element linear array of patch antennas, direct-conversion receivers and a Xilinx Virtex-6 FPGA based real-time digital back-end clocked at 240 MHz are described as an example realization of 16 complex-valued (IQ) receive-mode RF beams, centered at 2.4 GHz with 120 MHz of bandwidth per beam.