研究目的
To analyze, design, and implement stacked transistors for power amplifiers on InP Double Heterojunction Bipolar Transistors (DHBTs) technology, focusing on interstage matching, large-signal effects, and layout-related limitations.
研究成果
The three- and four-stacked transistors power cells implemented and measured in small- and large-signal operation showed comparable saturated output power, with the three-stacked transistor exhibiting higher peak PAE due to lower bias voltage. The four-stacked power cell showed better small-signal gain performances. The three-stacked transistor was selected for a four-way combined power stage, demonstrating a linear gain of 8.1 dB and a saturated output power higher than 18 dBm.
研究不足
Layout-related parasitic effects, finite length of interconnects introducing phase misalignment between collector voltages, resulting in early compression.