研究目的
To report experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs featuring a unique gate-stacking heterostructure produced in a self-organization approach, aiming to achieve superior gate modulation and high ON-OFF drain current ratio.
研究成果
The study successfully demonstrates the fabrication of Si0.15Ge0.85 n-MOSFETs with a unique gate-stacking heterostructure, achieving superior gate modulation and high ON-OFF drain current ratio. The self-organized approach enables the simultaneous production of the heterostructure in a single oxidation step, offering a promising pathway for advanced Ge-based MOS nanoelectronic and nanophotonic devices.
研究不足
The study is limited by the sensitivity of the fabrication process to thermal budgets and the challenge of achieving high-quality Ge MOSFETs over Si substrates due to lattice mismatch and gate-oxide integrity issues.
1：Experimental Design and Method Selection:
The study involves the fabrication of Si0.15Ge0.85 n-MOSFETs with a gate-stacking of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate using a self-organization approach. The heterostructure is produced in a single oxidation step controlled by the dynamic balance between oxygen, Si, and Ge interstitials at 900oC.
2：15Ge85 n-MOSFETs with a gate-stacking of Ge-nanospherical gate/SiO2/Si15Ge85-nanosheet on SOI (100) substrate using a self-organization approach. The heterostructure is produced in a single oxidation step controlled by the dynamic balance between oxygen, Si, and Ge interstitials at 900oC. Sample Selection and Data Sources:
2. Sample Selection and Data Sources: The samples are fabricated on SOI (100) substrates with a tri-layer of Si3N4/poly-Si0.85Ge0.15/SiO2. Data is collected through electrical characterization of the fabricated devices.
3：85Ge15/SiOData is collected through electrical characterization of the fabricated devices. List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: SOI (100) substrates, Si3N4, poly-Si0.85Ge0.15, SiO2, thermal oxidation equipment, lithography tools, plasma etching equipment, ion implantation equipment, and electrical measurement systems.
4：85Ge15, SiO2, thermal oxidation equipment, lithography tools, plasma etching equipment, ion implantation equipment, and electrical measurement systems. Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: The process includes deposition of the tri-layer, lithographic patterning of a poly-Si0.85Ge0.15 nano-pillar, thermal oxidation, S/D delineation, phosphorous ion implantation, passivation SiO2 deposition, gate contact-hole patterning, in situ phosphorous-doped poly-Si layer deposition, and final device fabrication steps including metallization and annealing.
5：85Ge15 nano-pillar, thermal oxidation, S/D delineation, phosphorous ion implantation, passivation SiO2 deposition, gate contact-hole patterning, in situ phosphorous-doped poly-Si layer deposition, and final device fabrication steps including metallization and annealing. Data Analysis Methods:
5. Data Analysis Methods: Electrical characterization data is analyzed to evaluate device performance, including subthreshold slope, ON-OFF current ratio, and transconductance.
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electrical measurement systems
Agilent B1500
Agilent
Used for characterizing the electrical performance of the fabricated devices.
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SOI (100) substrate
Used as the base substrate for fabricating the Si0.15Ge0.85 n-MOSFETs.
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Si3N4
Used as a buffer layer in the tri-layer deposition process.
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poly-Si0.85Ge0.15
Used in the fabrication of the nano-pillar for the gate-stacking heterostructure.
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SiO2
Used as part of the gate oxide and passivation layer in the device fabrication.
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thermal oxidation equipment
Used for the oxidation step to form the gate-stacking heterostructure.
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lithography tools
Used for patterning the poly-Si0.85Ge0.15 nano-pillar.
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plasma etching equipment
Used for S/D delineation and etching processes.
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ion implantation equipment
Used for doping the S/D regions with phosphorous ions.
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