研究目的
To detail the characteristics of a recently developed front-end application specific integrated circuit (ASIC) designed for high-purity germanium (HPGe) strip detectors.
研究成果
The ASIC meets the readout requirements for a germanium strip detector, providing low-noise amplification, peak detection and timing with analog memory, and sparsification. Preliminary results from an updated board design show promising improvements in ENC and timing resolution.
研究不足
The ASIC's performance may be affected by board layout or power regulation flaws, as indicated by higher noise levels at certain gain settings. The timing resolution degradation at small input capacitance is not fully understood and may be due to board and power issues.
1：Experimental Design and Method Selection:
The ASIC was designed to handle the large capacitance of germanium strip detectors while achieving low noise and high energy resolution. It includes a low-noise charge amplifier, a shaper with stabilized baseline, a programmable discriminator, a Time-to-Amplitude circuit (TAC), and a peak detector with analog memory.
2：Sample Selection and Data Sources:
The ASIC was tested with an internal test pulser and external pulsers to inject charge into the preamplifier. A surface mount 1 pF capacitor was used to calibrate the internal pulser.
3：List of Experimental Equipment and Materials:
The test setup included Agilent 33250A pulse generators, a test board manufactured from Rogers 4350B, and Analog Devices AD7680 16-bit ADCs.
4：Experimental Procedures and Operational Workflow:
The ASIC's response to charge input pulses was measured for all peaking times and gain settings. The gain and equivalent noise charge (ENC) were measured as functions of input capacitance.
5：Data Analysis Methods:
The data obtained from the readout board was histogrammed, and a gaussian was fit to the peak from the injected signals to determine the gain and ENC.
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