研究目的
Investigating the integration of graphene with Si technologies for electronic and optoelectronic applications.
研究成果
The study demonstrates key process modules for integrating graphene with Si technologies, highlighting the importance of encapsulation and low-resistance metal-graphene contacts. However, further improvements are needed to increase device yield and reduce variability.
研究不足
Challenges include graphene uniformity after transfer, process-related contaminations, and poor adhesion/delamination of graphene during various processing steps.
1：Experimental Design and Method Selection:
The study focuses on the integration of graphene into a 200 mm wafer Si technology environment, utilizing processes such as cleaning, patterning, encapsulation, and contacting.
2：Sample Selection and Data Sources:
Graphene was deposited by CVD on 200-mm Ge(100)/Si(100) wafers and transferred using electrochemical delamination method.
3：List of Experimental Equipment and Materials:
Equipment includes Aixtron’s Black Magic BM300T CVD tool, KLA-Tencor Spectra Fx200 wafer metrology tool, Renishaw In-Via system for Raman spectroscopy, Park NX20 system for AFM, and Applied Materials DxZ for silicon nitride deposition.
4：Experimental Procedures and Operational Workflow:
The process involves graphene transfer, encapsulation with SiN/SiO2, contact window etch, and metal-graphene contact formation.
5：Data Analysis Methods:
Spectroscopic ellipsometry, Raman spectroscopy, and electrical characterization were used for analysis.
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