研究目的
To automate the retrieval of interconnection information from delayered Integrated Circuits (IC) images using a robust and accurate machine learning based hierarchical multi-classifier system.
研究成果
The proposed hierarchical multi-classifier system achieved high accuracy in contact detection and poly line segmentation, significantly outperforming conventional methods. It offers a robust solution for automated analysis of delayered IC images.
研究不足
The system's performance may vary with different IC processes and camera settings, requiring sample recollection and classifier retraining for new ICs with different image features.
1：Experimental Design and Method Selection:
The study employs a hierarchical multi-classifier system (HMCS) for poly line segmentation and contact detection in delayered IC images. The methodology includes defining a poly line shape library, training binary classifiers for each shape, and applying these classifiers to detect shapes in IC images.
2：Sample Selection and Data Sources:
Samples are collected from delayered IC images for training classifiers. The study uses 50 SEM images of dimension 1536 × 2048 pixels for evaluation.
3：List of Experimental Equipment and Materials:
Scanning Electron Microscope (SEM) for imaging delayered ICs.
4：Experimental Procedures and Operational Workflow:
The process involves defining a poly line shape library, collecting samples for each shape, training binary classifiers, applying classifiers to detect shapes in IC images, and merging detected regions to form complete poly lines.
5：Data Analysis Methods:
Performance is evaluated using mean precision, mean recall, mean F-score for contact detection and differentiation, and mean intersection-over-union (IoU) and mean pixel accuracy for poly line segmentation.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
