研究目的
Investigating the reduction of power loss in circuit operation through accurate prediction of device-level power loss and the development of a compact modeling approach that includes non-ideal effects.
研究成果
The research demonstrates that a compact model development for accurate prediction of power losses can be achieved by considering all effects disturbing the MOSFET gate control. It highlights the importance of optimizing devices to improve gate controllability and circuit operation conditions for power-efficient design.
研究不足
The study focuses on MOSFETs and their descendants, potentially limiting its applicability to other semiconductor devices. The complexity of accurately modeling all non-ideal effects may also pose challenges.
1：Experimental Design and Method Selection:
The study employs a surface-potential-based compact modeling approach for MOSFETs, extending it to include non-ideal effects.
2：Sample Selection and Data Sources:
The research utilizes MOSFETs and their descendants, including power MOSFETs like LDMOS, for analysis.
3：List of Experimental Equipment and Materials:
Not explicitly mentioned.
4：Experimental Procedures and Operational Workflow:
The methodology involves solving the Poisson equation iteratively to model device characteristics and includes effects like short-channel and mobility reduction.
5：Data Analysis Methods:
The study compares model calculations with 2D-device simulation results and measured switching characteristics to verify model reliability.
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