研究目的
To propose a methodology for extracting the thermal equivalent circuit of a high density GaN-based power stage and to demonstrate the impact of adding a heatsink to a 48-to-12 V GaN-based buck converter.
研究成果
The proposed thermal solution, consisting of a heatsink, thermal interface pad, liquid gap filler, and Nylon shim, improved the current-handling capability by over 60%, enabling up to 200 W output power from the 3.7 cm2 power stage. This methodology can be applied to very high density designs where temperature sensing may be inaccurate or impractical.
研究不足
The methodology requires accurate measurement of Rds,on and may be limited by the accuracy of temperature measurements in high-density designs. The thermal model's accuracy depends on the calibration of the Rds,on-Tj relationship for each FET.
1：Experimental Design and Method Selection:
The methodology involves using a 48 V to 12 V GaN-based synchronous buck converter as the test platform to calculate junction temperatures by measuring Rds,on for both FETs in the half bridge. Current sources produce power losses in each device and the output filter inductor. Independent control of the two gate voltages allows for either symmetric or asymmetric distribution of power loss between the two FETs.
2：Sample Selection and Data Sources:
The test platform consists of two EPC2045 eGaN FETs, a gate driver IC, an output filter inductor, and other required passive components.
3：List of Experimental Equipment and Materials:
Equipment includes precision voltmeters, current sources, and an infrared thermal camera. Materials include a bare PCB, heatsink, gap pad, gap filler, and a plastic shim.
4：Experimental Procedures and Operational Workflow:
The test involves measuring Rds,on for both FETs under symmetric and asymmetric power loss distributions, and characterizing the thermal interaction with the filter inductor. The thermal design is tested with three air flow conditions.
5：Data Analysis Methods:
The thermal resistances are calculated from the test results to model the temperature of both FETs and the inductor based on the power loss dissipated by these components.
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