研究目的
Investigating the electrodeposition process for void-free bottom-up filling of sub-millimeter scale through silicon vias (TSVs) with Cu for MEMS technology.
研究成果
The study successfully demonstrated a robust electrodeposition process for void-free bottom-up filling of large scale TSVs with Cu, using a single-additive acid sulfonic acid chemistry. The process achieved a plating rate of nearly 100 μm/hr, with potential for optimization in galvanostatic control for full wafer plating.
研究不足
The study focuses on a specific size and aspect ratio of TSVs. The impact of convective contributions on the uniformity of TSV filling requires further attention for wafer-scale applications.
1：Experimental Design and Method Selection:
The study utilized an electrodeposition process under potentiostatic control for filling TSVs with Cu. The electrolyte composition and additive concentrations were optimized for selective suppression of metal deposition on the free surface and side walls.
2：Sample Selection and Data Sources:
TSVs with 600 μm depth and 125 μm diameter were used. The samples were prepared by back side etching of vias across a 600 μm thick wafer.
3：List of Experimental Equipment and Materials:
A polished Pt rotating disk electrode (RDE) was used for voltammetry. The electrolyte comprised 1.25 mol/L CuSO4, 0.25 mol/L CH3SO3H, with polyether and halide additions.
4：25 mol/L CuSO4, 25 mol/L CH3SO3H, with polyether and halide additions.
Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: The samples were rotated at 400 rpm during electrodeposition. Pre-wetting with low surface tension solvents was employed to ensure electrolyte wetting of the TSVs.
5：Data Analysis Methods:
Optical imaging and voltammetry were used to analyze the deposition process and the quality of the Cu filling.
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