研究目的
To design a referenceless clock and data recovery circuit with a bidirectional frequency detector to eliminate harmonic locking and reduce frequency acquisition time over a wide data rate range from 200 Mb/s to 3.2 Gb/s.
研究成果
The proposed referenceless CDR circuit with a bidirectional frequency detector successfully achieves a wide data rate range from 200 Mb/s to 3.2 Gb/s, with reduced frequency acquisition time of 11.8 μs and low jitter of 11 ps at 3 Gb/s. It eliminates harmonic locking and does not depend on external reference clocks or specific data patterns, making it suitable for various high-speed interface applications. Future work could involve physical implementation and testing in more advanced technology nodes.
研究不足
The operating data range is limited by the frequency range of the VCO. The study is based on simulation in a 180 nm CMOS process, which may not fully capture real-world variations or higher-frequency performance. The FD design may have dependencies on input data patterns, though it aims to be independent of run-length and transition density.
1：Experimental Design and Method Selection:
The study uses a half-rate clock and data recovery (CDR) circuit design based on a phase-locked loop (PLL) with a proposed bidirectional frequency detector (FD) and frequency band selector (FBS) for a voltage-controlled oscillator (VCO). The method involves simulation in a 180 nm CMOS process to evaluate performance.
2：Sample Selection and Data Sources:
The input data is a pseudorandom bit sequence (PRBS) with a length of 2^7 - 1, used for testing the CDR circuit across different data rates.
3：List of Experimental Equipment and Materials:
The circuit is implemented using CMOS technology; specific equipment includes simulation tools (not named), but no physical devices are listed as it is a simulation-based study.
4：Experimental Procedures and Operational Workflow:
The CDR circuit operates by first using the FBS to select the VCO frequency band based on the input data rate. The bidirectional FD detects frequency errors and adjusts the VCO frequency bidirectionally. A frequency lock detector (FLD) triggers a switch to phase detection mode once frequency is locked. Simulations are conducted to measure jitter and acquisition time.
5：Data Analysis Methods:
Performance metrics such as peak-to-peak jitter and frequency acquisition time are measured through simulation. Calculations based on theoretical models (e.g., equations for frequency deviation) are compared with simulation results.
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