研究目的
To develop digital circuit methods for correcting fixed pattern noise and filtering salt-and-pepper noise in nonlinear CMOS image sensors in hard real time.
研究成果
The paper successfully develops and validates digital circuit methods for FPN correction and SPN filtering in nonlinear CMOS image sensors, demonstrating efficiency and scalability to FHD video processing. The circuits are effective and efficient, with low resource usage and power consumption, providing benchmarks for future designs.
研究不足
The methods are validated using FPGA implementations, which may not fully represent ASIC performance. The study focuses on monochromatic sensors and does not address color filter arrays. Scalability to higher resolutions beyond 4K UHD is not tested, and power consumption evaluations are specific to the chosen low-cost FPGA devices.
1：Experimental Design and Method Selection:
The study uses a generic FPGA design flow with automated VHDL code generation from design templates and parameters processed via Matlab. Digital circuits are designed for FPN correction using inverse polynomial regression and for SPN filtering using median filtering with adaptive windows.
2：Sample Selection and Data Sources:
Experimental data from a logarithmic CMOS image sensor prototype with 48x64 pixels is used for validation.
3：List of Experimental Equipment and Materials:
FPGA tools from Xilinx (ISE
4：7) and Altera (Quartus 0), targeting devices Xilinx XC6SLX4 and Altera EP3CMatlab for scripting and simulation. Experimental Procedures and Operational Workflow:
Circuits are generated, simulated functionally and timing-wise, and evaluated for complexity, max frequency, and power consumption. Validation involves manual signal analysis and automatic comparison with software algorithms.
5：Data Analysis Methods:
Complexity is measured in logic elements and memory bits; max frequency is determined via static timing analysis; power consumption is decomposed into static and dynamic components using FPGA tools.
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