研究目的
To improve the isolation between transmitter and receiver in radar transceivers by designing an integrated full duplexer using a phase locked loop (PLL) to track antenna impedance variations in real time.
研究成果
The proposed full duplexer with PLL successfully improves isolation between transmitter and receiver by up to 45 dB through real-time impedance tracking. It consumes 79.5 mW DC power and occupies 0.495 mm2 area, demonstrating feasibility for radar applications with potential for further optimization in power and size.
研究不足
The study is limited to a specific 60nm RF CMOS fabrication process, and the design may face challenges with broader frequency bands or different antenna types. The use of an external active balun for measurement could introduce additional variables.
1：Experimental Design and Method Selection:
The study designs an integrated full duplexer with a PLL system to enhance isolation by tracking impedance variations. It employs a balance network and PLL components including a phase detector, charge pump, loop filter, bit controller, up/down counter, and tunable capacitor.
2：Sample Selection and Data Sources:
The duplexer is fabricated using 60nm RF CMOS technology, and measurements are conducted on the fabricated chip and PCB.
3：List of Experimental Equipment and Materials:
The chip is fabricated in 60nm RF CMOS process, and a PCB is used for measurement with an active balun for differential output ports.
4：Experimental Procedures and Operational Workflow:
The chip is wire-bonded on a PCB, and measurements are performed to assess transmitter leakage and isolation. The PLL system detects phase differences and adjusts capacitance in the balance network.
5：Data Analysis Methods:
Measurements include gain, CMRR, bandwidth, DC power consumption, and isolation levels, with results plotted against control voltage variations.
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D-flip flop
D-FF
Used in the phase detector to detect the rising edge of signals for phase comparison.
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NAND gate
Used in the phase detector and bit controller for logic operations.
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NOR gate
Used in the bit controller and up/down counter for logic operations.
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Inverter
Used in various components for signal refining and logic operations.
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Charge pump
Detects phase differences and adjusts control voltage by charging or discharging capacitors.
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Loop filter
Acts as a low-pass filter and charge collector in the PLL system.
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JK flip-flop
Used in the up/down counter for counting operations based on control bits.
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AND gate
Used in the up/down counter for logic operations.
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Tunable capacitor
25fF/step
Placed in the balance network to adjust capacitance for impedance matching.
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Active balun
Used externally for accurate measurement of differential output ports.
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CMOS process
60nm RF
Fabrication technology used for the integrated circuit.
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