研究目的
To address the challenges in PDK development due to transistor scaling limitations and new process technologies by introducing Agile PDK, a new modeling solution that enables DTCO activities, reduces development time, and improves model accuracies and MHC.
研究成果
The Agile PDK solution successfully addresses chronic PDK problems, improving model accuracy (max error <3%), reducing TAT by up to 50%, and enhancing MHC. It enables efficient DTCO activities and robust circuit designs, positioning it as a next-generation modeling standard.
研究不足
The paper does not explicitly mention specific limitations, but it implies challenges such as dependence on modeler expertise, trade-offs between model quality and development cost, and the complexity of non-convex optimization problems.
1：Experimental Design and Method Selection:
The study introduces Agile PDK with advanced algorithms including full binning, regression, and optimization to automate and improve PDK modeling. It involves parallel processing and user-defined regression in API for SPICE models.
2：Sample Selection and Data Sources:
Applied to the latest DRAM technology, using TEG (Test Element Group) matrices and silicon data from semiconductor fabrication processes.
3：List of Experimental Equipment and Materials:
Not specified in the paper.
4：Experimental Procedures and Operational Workflow:
Steps include full binning of device targets, automated parameter extraction using optimization algorithms (e.g., stochastic and iterative optimizers), and regression to connect binned targets via API. TCAD evaluations are used for corner devices.
5：Data Analysis Methods:
Optimization algorithms minimize cost functions for model parameter extraction, with results analyzed for accuracy (e.g., fitting errors around 3%) and MHC improvements.
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