研究目的
Designing a novel power clamp circuit with lower leakage current and smaller layout area for ESD protection in advanced SOI BCD processes.
研究成果
The proposed power clamp circuit achieves a sevenfold increase in BigFET turning on time to 591ns, reduces layout area by replacing a capacitor with a diode string, and exhibits low leakage current and high immunity to false triggering, demonstrating excellent ESD performance.
研究不足
The study is based on simulations in a specific 0.18μm SOI BCD process; experimental validation in physical devices and other process technologies may be needed for broader applicability.
1：Experimental Design and Method Selection:
The study involves designing a novel power clamp circuit using a diode string for detection and feedback technology to enhance triggering. Simulations are conducted to compare with traditional circuits.
2：Sample Selection and Data Sources:
Simulations are performed using Cadence Spectre in a 0.18μm SOI BCD process.
3：18μm SOI BCD process.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: Cadence Spectre simulator, specific device sizes as listed in Table I (e.g., resistors, diodes, transistors).
4：Experimental Procedures and Operational Workflow:
Simulate the circuit under 2000V HBM ESD stress, normal power-on conditions, and power noise pulses to evaluate performance metrics like turning on time and leakage current.
5：Data Analysis Methods:
Analyze simulation results to determine BigFET gate voltage, turning on time, and leakage current, comparing proposed and traditional circuits.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
