研究目的
To realize high-bandwidth, large-capacity NAND flash memory-based storage systems by developing a novel daisy-chain downlink interface that reduces power consumption and improves throughput.
研究成果
The proposed SCM2-based downlink I/F successfully achieves high bandwidth and large capacity with low power consumption, enabling efficient handling of 32 NAND packages at 12.8 Gb/s. It overcomes limitations of conventional topologies and demonstrates feasibility for future storage systems, though uplink applications need further research.
研究不足
The SCM2 technique is currently applied only to downlink interfaces; uplink applications require additional solutions. The architecture may face challenges in scaling to larger numbers of packages or higher data rates without further optimization.
1：Experimental Design and Method Selection:
The paper proposes a daisy-chain architecture with a tapered-bandwidth design and bridge-by-bridge selective data extraction using the SCM2 technique. It involves multiplexing and demultiplexing signals to handle multiple NAND packages efficiently.
2：Sample Selection and Data Sources:
The experiment uses fabricated prototype chips in a TSMC 28-nm CMOS process, with test setups involving motherboards, daughter boards, and a NAND board connected via stacking connectors.
3：List of Experimental Equipment and Materials:
Includes test chips, motherboards, daughter boards, NAND board, FPGA, stacking connectors, and measurement instruments like oscilloscopes and ADCs for monitoring.
4：Experimental Procedures and Operational Workflow:
The transceiver architecture is implemented with key components like HWPS and IBIC. Measurements involve generating and transmitting SCM2 signals, receiving and demodulating them in bridge chips, and evaluating BER and power consumption.
5：Data Analysis Methods:
BER is measured to assess performance, and power consumption is quantified. Constellation diagrams and eye diagrams are analyzed to verify signal integrity.
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