研究目的
To fabricate high-performance self-aligned top-gate thin film transistors with a dual-channel structure composed of In2O3 and IGZO layers to improve electrical characteristics such as mobility and threshold voltage control.
研究成果
The dual-channel TFTs exhibit significantly improved mobility (34.3 cm2/Vs) compared to single-layer a-IGZO TFTs (10.2 cm2/Vs), with a negative threshold voltage (-3.35 V), good subthreshold swing (0.44 V/decade), and high on/off current ratio (10^6). The devices show excellent spatial uniformity, indicating that the thin In2O3 layer remains amorphous and does not degrade performance. This approach is promising for high-speed, high-resolution display applications.
研究不足
The use of thin In2O3 films to avoid crystallization and negative threshold voltage issues may limit further mobility enhancements; the process is specific to self-aligned top-gate structures and may not be directly applicable to other TFT architectures.
1：Experimental Design and Method Selection:
The experiment involves fabricating self-aligned top-gate dual-channel TFTs on a glass substrate using sputtering and PECVD techniques, with a focus on comparing performance to single-layer a-IGZO TFTs. Theoretical models include equations for field-effect mobility and subthreshold swing.
2：Sample Selection and Data Sources:
A 2-inch glass substrate is used. Samples include TFTs with dual-channel (IGZO and In2O3 layers) and single-layer a-IGZO for comparison.
3：List of Experimental Equipment and Materials:
Equipment includes direct current sputtering system for depositing a-IGZO and In2O3 films, PECVD for SiO2 deposition, dry etching tools, plasma treatment systems (N2O and Ar plasma), and annealing furnace. Materials include glass substrate, a-IGZO, In2O3, SiO2, molybdenum (Mo) for gate and electrodes, hydrochloric acid for etching.
4：Experimental Procedures and Operational Workflow:
Process flow: Deposit 40 nm a-IGZO and 5-6 nm In2O3 by sputtering; pattern with hydrochloric acid etch; treat with N2O plasma; deposit 200 nm SiO2 gate insulator by PECVD; anneal at 300°C in O2; deposit and pattern Mo gate and SiO2; treat source/drain with Ar plasma; deposit 200 nm SiO2 passivation; pattern contact holes; deposit and pattern Mo source/drain electrodes by lift-off.
5：Data Analysis Methods:
Electrical properties (mobility, threshold voltage, subthreshold swing) are calculated using standard equations from transfer characteristics. Uniformity is assessed by testing multiple devices across the substrate.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
