研究目的
To control the threshold voltage (Vth) for low-voltage (5 V) operation in organic field-effect transistors (OFETs) using double gate dielectric layers composed of poly(vinyl cinnamate) and SiO2.
研究成果
The control of Vth was achieved in low-voltage operating OFET using double gate dielectric layers of PVCN and SiO2, with a driving voltage of -5 V and Vth shift of approximately 1.0 V. The programmed Vth was highly stable, with over 99% retention after 10^4 s, projecting 95% retention after 10^5 s. This approach is promising for developing novel sensors or circuits with low-voltage OFETs.
研究不足
The study does not discuss specific limitations, but potential areas for optimization could include further reducing operating voltage, improving stability beyond 10^5 s, and scaling for practical applications. The correlation between interface trap states (Nit) and ΔN requires further investigation.
1：Experimental Design and Method Selection:
The study uses a double gate dielectric layer approach with poly(vinyl cinnamate) (PVCN) and SiO2 to achieve low-voltage operation and Vth control in OFETs. The method involves charge trapping at the interface of the dielectric layers through a programming process with applied bias.
2：Sample Selection and Data Sources:
Devices were fabricated on heavily doped n-type silicon wafers with a 400-nm-thick SiO2 layer. Materials include PVCN, Ag electrodes, pentafluorothiophenol (PFBT), and a semiconductor layer of TIPS-pentacene and polystyrene (PS).
3：List of Experimental Equipment and Materials:
Silicon wafers, SiO2, PVCN solution (5 wt% in chlorobenzene), UV light source (λ = 365 nm), Ag for electrodes, PFBT, TIPS-pentacene, PS, Keithley 4200 semiconductor characterization system.
4：Experimental Procedures and Operational Workflow:
Clean wafer with ultrasonication in acetone, pure water, isopropanol, and UV-O3 treatment. Spin-coat PVCN layer, expose to UV for photocrosslinking, dry at 140°C. Thermally evaporate Ag electrodes, modify with PFBT. Spin-coat TIPS-pentacene/PS active layer. Perform electrical measurements with Keithley 4200, apply programming voltage (Vpro) from -10 V to -80 V for 3 s with source and drain grounded.
5：Data Analysis Methods:
Calculate Vth shift (ΔVth) and number of trapped holes (ΔN) using ΔN = Vth * Ci / q, where Ci is capacitance per unit area (7.9 nF/cm2) and q is elementary charge. Analyze retention characteristics using relative change of Vth over time.
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