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oe1(光电查) - 科学论文

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出版时间
  • 2018
研究主题
  • contrast stretch
  • CMOS image sensor
  • point-of-care (POC) diagnosis
  • bio-microfluidic imaging
应用领域
  • Optoelectronic Information Science and Engineering
机构单位
  • Xi’an University of Technology
183 条数据
?? 中文（中国） ▾

  • [IEEE 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Bangalore, India (2018.9.19-2018.9.22)] 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Effects of Memristors on Fully Differential Transimpedance Amplifier Performance

    摘要： The progress of the Internet of Things(IoT) technologies and applications requires the ef?cient low power circuits and architectures to maintain and improve the performance of the increasingly growing data processing systems. Memristive circuits and substitution of energy-consuming devices with memristors is a promising solution to reduce on-chip area and power dissipation of the architectures. In this paper, we proposed a CMOS-memristive fully differential transimpedance ampli?er and assess the impact of memristors on the ampli?er performance. The fully differential ampli?ers were simulated using 180nm CMOS technology and have 5.3-23MHz bandwidths and 2.3-5.7k? transimpedance gains with a 1pF load. We compare the memristor based ampli?er with conventional architecture. The gain, frequency response, linear range, power consumption, area, total harmonic distortion and performance variations with temperature are reported.

    关键词： transimpedance ampli?er,fully differential,180nm CMOS,IoT,memristor

    更新于2025-09-09 09:28:46

  • Epitaxial Bonding and Transfer Processes for Large-Scale Heterogeneously Integrated Electronic-Photonic Circuitry

    摘要： A process ?ow for the heterogeneous integration of III-V epitaxial material onto a silicon host wafer using CMOS-compatible materials and methods toward the goal of forming electronic-photonic circuitry is presented. Epitaxial structures for compound-semiconductor-based transistors are assembled on a silicon carrier wafer using a commercially-available polymer and then formed into distinct patterns for scalable processing. A CMOS-compatible metallization process is performed on the back side collector terminal of the aligned epitaxial structures, followed by a metal-eutectic bonding process that transfers the wafer-scale array of III-V material onto a separate silicon host wafer allowing the fabrication of both electronic and photonic devices on a single wafer. Characterization of the epitaxial bonding and transfer is performed to ensure material alignment is maintained without additional tooling and that the interconnect layer established between III-V collector and silicon host wafer performs as an ohmic contact, thermal path, and mechanical bond compatible with back-end-of-line (BEOL) integrated circuit processing. These processes are shown for GaAs-based light-emitting transistor (LET) epitaxial material to demonstrate that subsequent photonic devices and systems may be patterned into the integrated material allowing a direct electrical interconnect to embedded CMOS-based electronic systems for new functionalities as electronic-photonic integrated circuitry.

    关键词： epitaxial bonding,silicon host wafer,metal-eutectic bonding,III-V epitaxial material,electronic-photonic circuitry,heterogeneous integration,CMOS-compatible

    更新于2025-09-09 09:28:46

  • Single electron transistors with e-beam evaporation of SiO <sub/>2</sub> tunnel barriers

    摘要： Recent work on fabricating metal-insulator-metal (MIM) single electron transistors (SETs) using deposited dielectrics shows promise for becoming a manufacturable process due to compatibility with modern CMOS processes. This process, the “rib-SET” process [V. Joshi, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 26, 2587 (2008); G. Karbasian, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 33 (2015)], features a self-aligned island and should allow for scaling SETs below 10 nm. However, one of the biggest roadblocks in realizing a high-quality SET with this process has been dif?culties in developing high-quality, low-noise, MIM tunnel junctions. In this work, the authors report Pt-SiO2-Pt MIM SETs with tunnel barriers deposited by e-beam evaporation as an alternative to atomic layer deposition. There are some challenges in the formation of tunnel barriers via e-beam evaporation that are addressed. It is expected that platinum has a negligible native oxide; however, there is a substantial resistance in as-deposited Pt-SiO2-Pt structures that can be reduced by over 5 orders of magnitude by subjecting the ?nished devices to an anneal in a hydrogen plasma, suggesting the presence of an interfacial platinum oxide. It is shown that this treatment not only increases the conductance through the SET, but that it is necessary for forming high conductance tunnel barriers that are desired for making low-noise SETs.

    关键词： single electron transistors,metal-insulator-metal,e-beam evaporation,SiO2 tunnel barriers,CMOS processes

    更新于2025-09-09 09:28:46

  • Evolution of Ultra-high-speed Image Sensors; 超高速度イメージセンサ;

    摘要： 2009 年のノーベル賞を受賞した Boyle と Smith が撮像に CCD が使えそうだと示唆したのは 48 年前である1)．その後のイメージセンサの進化は目覚しく，空間解像度や感度は限界に近付きつつある．最先端のイメージセンサの画素サイズは(cid:9873)μm 近くに，量子効率（発生電子数／入射光子数）は 0.8 以上に，ノイズレベルは 1 photon 以下にまで小さくなった．今やイメージセンサを使わない可視化技術はないと言って良い．細密な空間分解能を要求されるホログラフィにおいてもデジタルホログラフィという呼び名でイメージセンサによる撮像が行われることが一般的になった．現在の技術であれば，フィルム用の銀塩粒子のサイズはナノメータ程度にまで小さくできるが，可視光の波長は 0.4μm?0.7μm であるからあまり小さくしても意味がない．一方，イメージセンサにおいても，シリコン結晶への緑色光の侵入深さは約(cid:9873)μm であり，赤色光に至っては(cid:9875)μm に達するから，画素サイズを(cid:9873)μm 以下にしても画素間のクロストークが過大になり，カラーイメージセンサでは色再現が困難になるだけである．一方，高速化についてはまだまだ進化の余地がある．本稿では高速度イメージセンサやビデオカメラについて進化の過程を俯瞰する．

    关键词： CMOS,3D接合型イメージセンサ,バーストイメージセンサ,超高速度イメージセンサ,CCD

    更新于2025-09-09 09:28:46

  • Hypersonic Surface Phononic Bandgap Demonstration in a CMOS-Compatible Pillar-Based Piezoelectric Structure on Silicon

    摘要： We demonstrate a new phononic crystal (PnC) platform with wideband hypersonic phononic bandgaps (PnBGs) for surface acoustic waves (SAWs). These SAW PnCs are fabricated on a CMOS-compatible substrate and constructed by a two-dimensional periodic array of piezoelectric aluminium nitride pillars on silicon to achieve a low-loss all-dielectric PnC platform. Our experimental PnBG results acquired with integrated wideband SAW ?lters (i.e., two slanted interdigital transducers as an emitter and a receiver) show a surface PnBG from 1.6 to 1.75 GHz for the fabricated surface PnC, enabling the formation of low-loss hypersonic PnC-based devices for a wide range of ultrahigh-frequency applications, including wireless communications.

    关键词： CMOS-compatible,phononic crystal,piezoelectric,hypersonic,surface acoustic waves

    更新于2025-09-09 09:28:46

  • Identification of Design Considerations for Small Satellite Remote Sensing Systems in Low Earth Orbit

    摘要： The Sergio Arboleda University is preparing its next satellite mission, named Libertad 2. It will carry out a system of image acquisition as a working tool for researches based on the obtained data. Complete methodologies are often used in the development of satellite missions for planning, execution and deployment, for example, the standards of the European Cooperation for Space Standardization; these methodologies, however, do not include technical specifications or requirements for the development of nano-satellites nor for their subsystems. For this reason, this article focuses on the identification of the characteristics, requirements and restrictions, which must be considered in the design of a remote sensing system for satellites under the CubeSat standard, in order to serve as a starting point for the development of the main payload of the Libertad 2 mission.

    关键词： CMOS APS,Embedded systems,Low earth orbit,Remote sensing,PCB,CubeSat

    更新于2025-09-09 09:28:46

  • Performance enhance of CMOS-MEMS thermoelectric infrared sensor by using sensing material and structure design

    摘要： This study presents the micro thermoelectric infrared sensor consisted of the heat material. Experiment results indicate the Detectivity of proposed design is 2-2.6 fold higher The proposed infrared absorber design has an umbrella-like structure with a post anchor to the TSMC 0.18μm 1P6M standard CMOS process and the in-house post-CMOS MEMS process. (infrared sensor consisted of only the serpentine structure with embedded thermocouple), a transduction absorber and the serpentine structure with embedded thermocouple using the serpentine suspension with embedded thermocouple. As compare with the reference design much higher Seebeck coefficient (56-fold), and is employed in this study as the thermocouple junctions is increased. Moreover, the umbrella-like structure has higher infrared absorption area with and without Silicide are respectively characterized. The poly-Si with no Silicide has a as compare with the serpentine structure. In addition, the Seebeck coefficients of poly-Si films better heat-flow path is achieved and the temperature difference between the hot and cold than that of the reference one at 200mtorr. Experiment also show that the responsivity enhancement of proposed design is further increased as the sensor size is reduced in area.

    关键词： thermoelectric,Seebeck effect,thermopile,CMOS-MEMS,infrared sensor

    更新于2025-09-09 09:28:46

  • [IEEE 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Qingdao, China (2018.10.31-2018.11.3)] 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Non-filamentary Pd/Al<inf>2</inf>O<inf>3</inf>/TaO<inf>x</inf>/Ta Memristor as Artificial Synapse for Neuromorphic Computing

    摘要： We report a fully CMOS compatible bilayer, forming-free and non-filamentary memristive device with excellent bidirectional analog switching behavior as artificial synapse for neuromorphic computing applications. The bilayer stack structure, consisting of 8 nm TaOx formed via oxidation process on Ta bottom electrode and 7 nm Al2O3 via atom layer deposition (ALD), is sandwiched between the Ta bottom electrode and Pd top electrode. The Pd/Al2O3/TaOx/Ta device shows bidirectional analog resistive switching behaviors, and multilevel conductance states (>60) with satisfying retention time can be obtained. Long term plasticity, consisting of long-term potentiation (LTP) and long-term depression (LTD), have been demonstrated based our device. And a nearly linear conductance change behavior is obtained by optimizing the training scheme: adopting non-identical training pulses. A two-layer perceptron neural network was performed to estimate the synapse characteristics of our devices. More than 94% recognition accuracy of MNIST handwritten digit dataset are achieved. Based on these results, the device is a promising emulator for biology synapse, and has a great potential to be used in neuromorphic systems.

    关键词： memristor,neuromorphic computing,analog switching,artificial synapse,CMOS compatible

    更新于2025-09-09 09:28:46

  • Optimization of CMOS Image Sensor Utilizing Variable Temporal Multi-Sampling Partial Transfer Technique to Achieve Full-frame High Dynamic Range with Superior Low Light and Stop Motion Capability

    摘要： Differential Binary Pixel Technology is a threshold-based timing, readout and image reconstruction method that utilizes sub-frame partial charge transfer technique in a standard four-transistor (4T) pixel CMOS Image sensor (CIS) to achieve HDR video with Stop Motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21dB. The method is verified in silicon using a TSMC 65nm 1.1μm pixel technology 1 megapixel (MP) test chip array and is compared with a traditional 4× oversampling technique using full charge transfer. The test chip is also compared with the iPhone 6s rear view camera to show superior HDR video capability.

    关键词： HDR video,iPhone 6s,Differential Binary Pixel Technology,SNR,CMOS Image sensor,Stop Motion,TSMC 65nm

    更新于2025-09-04 15:30:14

  • A CMOS-Based Thermopile Array Fabricated on a Single SiO2 Membrane

    摘要： We present a novel thermopile-based infrared (IR) sensor array fabricated on a single CMOS dielectric membrane, comprising of poly-silicon p+ and n+ elements. Processing of the chip is simplified by fabricating the entire array on a single membrane and by using standard CMOS Al metal layers for thermopile cold junction heatsinking. On a chip area of 1.76 mm × 1.76 mm, with a membrane size of 1.2 mm × 1.2 mm, we fabricated IR sensor arrays with 8 × 8 to 100 × 100 pixels. The 8 × 8 pixel device has <2% thermal crosstalk, a responsivity of 36 V/W and enhanced optical absorption in the 8–14 μm waveband, making it particularly suitable for people presence sensing.

    关键词： IR image sensor,presence sensing,thermopile array,MEMS,infrared,CMOS

    更新于2025-09-04 15:30:14