- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Opportunities for High Efficiency Monochromatic Photovoltaic Power Conversion at 1310 nm
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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[IEEE 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Kolkata, India (2019.8.29-2019.8.31)] 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Effect of I Shaped Periodic Structures over Collinear Arms of 150 Degree Bend Substrate Integrated Waveguide
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Beijing, China (2019.11.21-2019.11.23)] 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Accurate Short-term Forecasting for Photovoltaic Power Method Using RBM Combined LSTM-RNN Structure with Weather Factors Quantification
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-23 15:19:57
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[IEEE 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Xiamen, China (2019.12.17-2019.12.20)] 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Microwave Approach to Study Resonant Features of All-dielectric Metasurfaces
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-19 17:13:59
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[IEEE 2019 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD) - Ottawa, ON, Canada (2019.7.8-2019.7.12)] 2019 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD) - Modeling phase noise in high-power photodetectors
摘要： Enterprises can save a signi?cant energy by letting idle desktops sleep and awake them only when needed. Though existing mechanisms based on centralized or distributed sleep proxy scheme address this issue with good availability, which means that a sleeping machine can always be awoken when needed, they still feature some drawbacks, such as dedicated per-subnet servers, additional per-desktop CPU resource utilization, and extra energy consumption. This seriously impedes their widespread deployment in enterprises. We, thus, propose an improved scheme called wake-up system based on cloud (WaSCO). WaSCO not only provides high availability but also consumes low CPU resource and energy, as it does not need any speci?c server to help achieve high availability. This system of?oads heavy computation from desktops to a stable cloud, which is responsible for managing agents in various subnets by using our proposed algorithm called choosing-and-guaranteeing (CGA) algorithm. When a remote user wakes up a desktop with WaSCO, the cloud sends a message to the selected agents in the subnet, which then send wake-on-LAN packets to wake up the target desktop. In essence, CGA algorithm ensures running agents in each subnet, dynamically adjusts the number of agents, and selects a few desktops, rather than all the desktops, as agents. Experimental results show that WaSCO outperforms centralized and distributed sleep proxy mechanisms in terms of deployment cost, CPU resource cost, and energy consumption, while still maintains high availability.
关键词： Wake-up,energy,cloud,CPU,availability
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Theoretical study of the MAPbI <sub/>3</sub> /SnO <sub/>2</sub> interface band offset in perovskite solar cells considering mobile ions
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59
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Fast UV-Curing Encapsulation for GaN-Based Light-Emitting Diodes
摘要： Enterprises can save a signi?cant energy by letting idle desktops sleep and awake them only when needed. Though existing mechanisms based on centralized or distributed sleep proxy scheme address this issue with good availability, which means that a sleeping machine can always be awoken when needed, they still feature some drawbacks, such as dedicated per-subnet servers, additional per-desktop CPU resource utilization, and extra energy consumption. This seriously impedes their widespread deployment in enterprises. We, thus, propose an improved scheme called wake-up system based on cloud (WaSCO). WaSCO not only provides high availability but also consumes low CPU resource and energy, as it does not need any speci?c server to help achieve high availability. This system of?oads heavy computation from desktops to a stable cloud, which is responsible for managing agents in various subnets by using our proposed algorithm called choosing-and-guaranteeing (CGA) algorithm. When a remote user wakes up a desktop with WaSCO, the cloud sends a message to the selected agents in the subnet, which then send wake-on-LAN packets to wake up the target desktop. In essence, CGA algorithm ensures running agents in each subnet, dynamically adjusts the number of agents, and selects a few desktops, rather than all the desktops, as agents. Experimental results show that WaSCO outperforms centralized and distributed sleep proxy mechanisms in terms of deployment cost, CPU resource cost, and energy consumption, while still maintains high availability.
关键词： CPU,energy,availability,Wake-up,cloud
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Flexible silicon heterojunction solar cells on 40 ?μm thin substrates
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59
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[IEEE 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Dresden (2018.3.19-2018.3.23)] 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Characterizing display QoS based on frame dropping for power management of interactive applications on smartphones
摘要： User-centric power management in smartphones aims to conserve power without affecting user’s perceived quality of experience. Most existing works focus on periodically updated applications such as games and video players and use a fixed frame rate, measured in frame per second (FPS), as the metric to quantify the display quality of service (QoS). The idea is to adjust the CPU/GPU frequency just enough to maintain the frame rate at a user satisfactory level. However, when applied to aperiodically-updated interactive applications, e.g. Facebook or Instagram, that draw the frame buffer at a varying rate in response to user inputs, such a power management strategy becomes too conservative. Based on real user experiments, we observe that users can tolerate a certain percentage of frame drops when running aperiodically updated applications without affecting their perceived display quality. Hence, we introduce a new metric to characterize display quality of service, called the frame drawn ratio (FDR), and propose a new CPU/GPU frequency governor based on the FDR metric. The experiments by real users show that the proposed governor can conserve 17.2% power in average when compared to the default governor, while maintaining the same or even better QoE rating.
关键词： user experience,smartphones,frame rate,CPU/GPU frequency scaling,Power management
更新于2025-09-11 14:12:44