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[IEEE 2018 25th IEEE International Conference on Image Processing (ICIP) - Athens, Greece (2018.10.7-2018.10.10)] 2018 25th IEEE International Conference on Image Processing (ICIP) - Gestalt Interest Points with a Neural Network for Makeup-Robust Face Recognition
摘要： In this paper, we propose a novel approach for the domain of makeup-robust face recognition. Most face recognition schemes usually fail to generalize well on these data where there is a large difference between the training and testing sets, e.g., makeup changes. Our method focuses on the problem of determining whether face images before and after makeup refer to the same identity. The work on this fundamental research topic benefits various real-world applications, for example automated passport control, security in general, and surveillance. Experiments show that our method is highly effective in comparison to state-of-the-art methods.
关键词： CNN,Face recognition,makeup-robust,GIP,person identification
更新于2025-09-23 15:21:01
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3.5: Optimization of LTPS‐AMOLED Array Design to Enhance the Resistance to ESD risk
摘要： Electrostatic discharge (ESD) is a significant cause of yield loss in FPD (Flat Panel Display) array manufacturing. LTPS-TFT Arrays processing includes a series of chucking and conveyance steps, in which, some of these steps would generate triboelectric charge [1, 2]. Although low-impedance materials for equipment contact parts with glass substrate have been adopted, and good grounding has been implemented, ESD still happens frequently. In order to understand the root-cause of ESD and to minimize the ESD effect, it is necessary to have a systematic research on LTPS-TFT Arrays processing. By studying and identifying the locations of ESD in different LTPS-AMOLED products, we found three ESD causes related to the different array designs as described below: 1: Overlap between adjacent metal layers is easy to generate ESD, e.g. the overlap of metal 1 line of EM and metal 2 jumper line of Vdata, the overlap of metal 1 jumper line of Vdata and metal 2 jumper line of VDD, the overlap of metal 2 line of Vref and metal 1 jumper line of Vdata. 2: Research on ESD in products’ GIP (Gate Driver in Panel) area indicates that the distance of Capacity C1/C2 in GIP-Scan circuit, D1 for short, and the area difference of C1/C2 have an obvious correlation with ESD, in which the products’ resistance to ESD risk is enhanced with the increase of D1 distance and the decrease of C1/C1 area difference. 3: Study of ESD in CT (Cell Test) area shows that CT ESD has a strong correlation with IC Pad, including COF Pad & IC output Pad, in which, ESD occurs easily when IC Pad is connected to CT circuit directly. By optimizing array design, products with excellent resistance to ESD risks can be obtained.
关键词： Overlay of Metal Line,CT Circuit,GIP Circuit,ESD,Array Design,LTPS-AMOLED
更新于2025-09-19 17:13:59