Hardware implementation of digital image skeletonization algorithm using FPGA for computer vision applications

摘要： This paper proposed a method for digital image skeletonization of 2-D image of size 8 (cid:1) 8 and its implementation on Field Programmable Gate Array (FPGA). The time required to execute the proposed algorithm for 8 (cid:1) 8 dimension image on FPGA recon?gurable hardware is 4.815 ns, maximum output required time after clock: 4.075 ns, maximum frequency: 207.684 MHz, minimum input arrival time before clock: 2.284 ns. These values are for Vertex 5 FPGA board. This proposed algorithm ?nds applications in pattern recognition, computer vision, image matching and so on. This method can used in real time image processing applications. This algorithm may be extended for 3-D images and FPGA architecture may be proposed accordingly.