- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[Springer Theses] Electrical Properties of Indium Arsenide Nanowires and Their Field-Effect Transistors || Introduction
摘要： As the miniaturization and integration of solid-state electronic devices has continued to increase rapidly with the demands of high speed, low power consumption and high storage density, the conventional Si-based technology has lost their advantages on fabrication process. Therefore the technologies based on new materials gradually attract researchers’ attention. Among them, Indium Arsenide (InAs) nanowires (NWs) with high electron mobility is one of the most promising candidate. In this chapter, we introduce the advantages of InAs nanowire on electronic devices and the development status of InAs nanowire electronic devices. Also, the topic ideas and chapter arrangements of this thesis are presented.
关键词： solid-state,high electron mobility,electronic devices,InAs nanowires,miniaturization
更新于2025-09-23 15:21:21
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<i>(Invited) The Scaling-Down and Performance Optimization of InAs Nanowire Field Effect Transistors</i>
摘要： Due to their fascinating properties, InAs nanowires have drawn great attention for the channel material in future transistors. Scaling-down has been an effective way to improve the performance of transistors continuously for decades. Here, we review our recent progresses on InAs nanowire field effect transistors (FETs) when they are scaled down. Our group investigates the electrical characteristics of InAs nanowire thinner than 10 nm. Both the size-effect and the contact properties of ultrathin nanowires are explored. Moreover, the effects of InAs crystal phase and orientation are studied for further optimizing the device performance. In addition, FETs with partial gate are studied to suppress the BTBT-induced off-current. Furthermore, to improve the electrostatics control of the gate, our group develops a method to fabricate vertical GAA FETs with all-metal electrodes based on self-catalyzed grown InAs nanowire arrays.
关键词： orientation,crystal phase,performance optimization,field effect transistors,partial gate,vertical GAA FETs,InAs nanowires,scaling-down
更新于2025-09-23 15:21:01
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Effect of stacking faults and surface roughness on the thermal conductivity of InAs nanowires
摘要： Low thermal conductivity and high power factor are desirable for thermoelectric materials. These properties can be achieved by patterning devices into nano-structures such as nanowires (NWs). The thermal conductivity can be further reduced by altering the NW geometry through the introduction of surface roughness (SR) or stacking faults (SFs). In this paper, relaxation times for scattering of phonons at SFs and SR are developed to accurately compute the impact of both effects on the thermal conductivity of InAs NWs with different diameters. It is found that similar reductions of the thermal conductivity can be obtained with SFs instead of SR. For the shortest possible distance between SFs along a NW, the room temperature thermal conductivity can be reduced to 25% compared to an ideal NW. For a NW with rough surface, a more than 80% decrease of the thermal conductivity is possible for specific roughness profiles. All available experimental data on the lattice thermal conductivity of InAs NWs confirm the theoretical models and simulation results.
关键词： surface roughness,thermal conductivity,phonon scattering,stacking faults,InAs nanowires
更新于2025-09-10 09:29:36