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InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities
摘要： III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 μA/μm and subthreshold slope of about 85 mV/dec.
关键词： Integration,MOSFETs,TASE,III-V
更新于2025-09-23 15:22:29
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Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs
摘要： In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant 'number' and dopant 'position' fluctuation in channels is proposed. A new model of σVth,num caused by 'number' is given and the method of obtaining the 'position' influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.
关键词： threshold voltage variation,analytical model,fully depleted silicon-on-insulator MOSFETs,Sentaurus TCAD simulation,random dopant fluctuation
更新于2025-09-23 15:22:29
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Contact Engineering for Dual-Gate MoS <sub/>2</sub> Transistors Using O <sub/>2</sub> Plasma Exposure
摘要： The benefits of O2 plasma exposure at the contact regions of dual-gate MoS2 transistors prior to metal deposition for high performance electron contacts is studied and evaluated. Comparisons between devices with and without the exposure demonstrate significant improvements due to the formation of a high-quality contact interface with low electron Schottky barrier (~0.1 eV). Topographical and interfacial characterization are used to study the contact formation on MoS2 from the initial exfoliated surface through the photolithography process and Ti deposition. Fermi level pinning near the conduction band is shown to take place after photoresist development leaves residue on the MoS2 surface. After O2 plasma exposure and subsequent Ti deposition, Ti scavenges oxygen from MoOx and forms TiOx. Electrical characterization results indicate that photoresist residue and other contaminants present after development can significantly impact electrical performance. Without O2 plasma exposure at the contacts, output characteristics of MoS2 FETs demonstrate non-linear, Schottky-like contact behavior compared to the linearity observed for contacts with exposure. O2 plasma allows for the removal of the residue present at the surface of MoS2 without the use of a high temperature anneal. A low conduction band offset and superior carrier injection are engineered by employing the reactive metal Ti as the contact to deliberately form TiO2. Dual-gate MoS2 transistors with O2 plasma exposure at the contacts demonstrate linear output characteristics, lower contact resistance (~20× reduction), and higher field effect mobility (~15× increase) compared to those without the treatment. In addition, these results indicate that device fabrication process induced effects cannot be ignored during the formation of contacts on MoS2 and other 2D materials.
关键词： TiO2,MoS2,contact resistance,O2 plasma,photoresist residue,MOSFETs,contacts
更新于2025-09-23 15:22:29
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Online Junction Temperature Extraction of SiC Power MOSFETs with Temperature Sensitive Optic Parameter (TSOP) Approach
摘要： Accurate information of the junction temperature of SiC power MOSFETs ensures safe operation and helps reliability assessment of the devices. In this paper, an online junction temperature extraction method is proposed based on the electroluminescence phenomenon of the body diode of SiC power MOSFETs. It is found that during the forward conduction interval of the body diode, visible blue light is emitted around the chip, which ascribes to the radiative recombination in the low doped region of SiC MOSFETs. Experimental results suggest the light intensity changes linearly with the variation of the temperature and behaves as a temperature sensitive optic parameter (TSOP). Further, an electro-thermal-optic model is proposed to reveal the relationship between electroluminescence intensity, forward current and junction temperature. Based on the TSOP, an online junction temperature extraction method is proposed for SiC MOSFETs and verified in a SiC MOSFET based inverter. Compared with state-of-the-art methods, the proposed junction temperature measurement method is contactless and immune from the aging of the package.
关键词： junction temperature extraction,Body diode,thermal management,electroluminescence,SiC MOSFETs
更新于2025-09-23 15:22:29
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GaN Transistors for Efficient Power Conversion || Resonant and Soft-Switching Converters
摘要： The previous chapter addressed the application of GaN transistors in hard-switching power converters, and we demonstrated the benefits that GaN transistors provide – as compared to state-of-the-art silicon power MOSFETs. In this chapter, we discuss the fundamentals of resonant and soft-switching applications and evaluate the superior performance capabilities of GaN transistors over silicon MOSFETs in these applications. The chapter will conclude with a design example comparing GaN transistors and Si MOSFETs in an isolated, high-frequency 48 V intermediate bus converter (IBC) with a 12 V output, utilizing a resonant topology operating at 1.2 MHz.
关键词： power conversion,GaN transistors,resonant converters,soft-switching,silicon MOSFETs
更新于2025-09-23 15:21:01
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[IEEE 2019 FISE-IEEE/CIGRE Conference - Living the energy Transition (FISE/CIGRE) - Medellin, Colombia (2019.12.4-2019.12.6)] 2019 FISE-IEEE/CIGRE Conference - Living the energy Transition (FISE/CIGRE) - Abating carbon emissions by means of utility-scale photovoltaics and storage: the Duke Energy Progress/Carolinas case study
摘要： A Sn-doped (100) β-Ga2O3 epitaxial layer was grown via metal–organic vapor phase epitaxy onto a single-crystal, Mg-doped semi-insulating (100) β-Ga2O3 substrate. Ga2O3-based metal–oxide–semiconductor field-effect transistors with a 2-μm gate length (L G), 3.4-μm source–drain spacing (LSD), and 0.6-μm gate–drain spacing (LGD) were fabricated and characterized. Devices were observed to hold a gate-to-drain voltage of 230 V in the OFF-state. The gate-to-drain electric field corresponds to 3.8 MV/cm, which is the highest reported for any transistor and surpassing bulk GaN and SiC theoretical limits. Further performance projections are made based on layout, process, and material optimizations to be considered in future iterations.
关键词： MOVPE,β-Ga2O3,MOSFETs,power semiconductor devices
更新于2025-09-23 15:19:57
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Device Physics, Modeling, Technology, and Analysis for Silicon MESFET || Modeling of Classical SOI MESFET
摘要： Since the advent of the ?rst integrated circuit, the downscaling trend has led to extensive progress regarding cost, performance, and level of integration. It is well known that development in the level of integration is achieved by continuous reduction of the minimum size of electronic components. However, since downscaling has encroached on submicron territory, some undesirable effects have begun to pull down the performance of transistors. Also, the technological problems related to shrinking junctions and growing high-integrity thin oxide layer are apparent. Hence, the reduction in physical dimensions needs to be concurrent with some other alterations like increasing of doping levels, reducing of insulator thickness, and decreasing of junction depth to degrade the second-order effects related to downscaling. When gate lengths are scaled and doping levels are increased, electric ?elds tend to rise. The higher electric ?eld, in small geometry devices, emitted the energetic carriers into the gate oxide layer and caused a shift in threshold voltage and therefore the reduction of transconductance with time (hot carrier effect). This problem can be lessened by reducing the junction electric ?eld which is obtained by the reduction of the source and drain doping concentrations. But, low-doped regions, especially in small geometry devices, bring some other disadvantages like the high contact resistance. Also, lightly doped drain (LDD) MOS devices are introduced to repress the hot carrier effects. In these devices, introducing a narrow, lightly doped n-type region between the channel and the drain and source areas, the doping pro?le of the drain and source is modi?ed. As a result, the electric ?eld in the pinch-off region and thus the hot carrier effect and also the impact ionization are reduced. However, LDD MOSFETs have some drawbacks including the degradation of the current drive due to the increasing resistance and more processing complexity of the device manufacturing. Another challenge of dimension downscaling relates to the ultra-thin oxide layer. The growing of high-quality and low-defect thin oxides is dif?cult. Moreover, quantum mechanical direct tunneling (QMDT) is an important disadvantage in the ultra-thin gate oxide which remarkably reduces the device performance. The last challenge is related to the junction depth scaling. The fact is that due to the various technological reasons, the junction depth has not been scaled pretty with scaling of channel lengths.
关键词： quantum mechanical direct tunneling,LDD MOSFETs,SOI MESFET,hot carrier effect,downscaling
更新于2025-09-23 15:19:57
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Fully-vertical GaN-on-Si power MOSFETs
摘要： We report the first demonstration of fully-vertical power MOSFETs on 6.6-μm-thick GaN grown on a 6-inch Si substrate by metal-organic chemical vapor deposition (MOCVD). A robust fabrication method was developed based on a selective and local removal of the Si substrate as well as the resistive GaN buffer layers, followed by a conformal deposition of a 35-μm-thick copper layer on the backside by electroplating, which provides excellent mechanical stability and electrical contact to the drain terminal. The fabrication process of the gate trench was optimized, improving considerably the effective mobility at the p-GaN channel and the output current of the devices. High performance fully-vertical GaN-on-Si MOSFETs are presented, with low specific on-resistance (Ron,sp) of 5 m?cm2 and high off-state breakdown voltage (BV) of 520 V. Our results reveal a major step towards the realization of high performance GaN vertical power devices on cost-effective Si substrates.
关键词： power devices,GaN,low Ron,sp,GaN-on-Si,fully-vertical,MOSFETs,vertical,high breakdown
更新于2025-09-19 17:15:36
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[IEEE 2019 International Semiconductor Conference (CAS) - Sinaia, Romania (2019.10.9-2019.10.11)] 2019 International Semiconductor Conference (CAS) - Voltage Controlled Oscillator for Small-Signal Capacitance Sensing
摘要： SiC MOSFETs are applied to constitute a three-phase, 5-kW LLC series resonant dc/dc converter with isolation transformers. A switching frequency of around 200 kHz for the transistors successfully reduces the volume of these isolation transformers, whereas insulated-gate bipolar transistors (IGBTs) are not capable of achieving such a high switching speed. The high-voltage tolerance of SiC MOSFETs, 1200 V, enables increasing the input voltage up to 600 V. High-voltage tolerance, on the other hand, is not compatible with low on-resistance for Si MOSFETs. A three-phase circuit topology is used to achieve up to 5 kW of power capacity for the converter and reduce per-phase current at the same time. Current-balancing transformers among these three phases effectively suppress a maximum peak current from arising in the circuit, a technique that miniaturizes the input and output capacitances. The conversion efficiency of the converter reaches 97.6% at 5-kW operation.
关键词： SiC MOSFETs,zero-voltage switching (ZVS),Current-balancing transformers,zero-current switching (ZCS),three phase,LLC resonant converter
更新于2025-09-19 17:13:59
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Perspective: Ga <sub/>2</sub> O <sub/>3</sub> for ultra-high power rectifiers and MOSFETS
摘要： Gallium oxide (Ga2O3) is emerging as a viable candidate for certain classes of power electronics with capabilities beyond existing technologies due to its large bandgap, controllable doping, and the availability of large diameter, relatively inexpensive substrates. These applications include power conditioning systems, including pulsed power for avionics and electric ships, solid-state drivers for heavy electric motors, and advanced power management and control electronics. Wide bandgap (WBG) power devices offer potential savings in both energy and cost. However, converters powered by WBG devices require innovation at all levels, entailing changes to system design, circuit architecture, qualification metrics, and even market models. The performance of high voltage rectifiers and enhancement-mode metal-oxide field effect transistors benefits from the larger critical electric field of β-Ga2O3 relative to either SiC or GaN. Reverse breakdown voltages of over 2 kV for β-Ga2O3 have been reported, either with or without edge termination and over 3 kV for a lateral field-plated Ga2O3 Schottky diode on sapphire. The metal-oxide-semiconductor field-effect transistors fabricated on Ga2O3 to date have predominantly been depletion (d-mode) devices, with a few demonstrations of enhancement (e-mode) operation. While these results are promising, what are the limitations of this technology and what needs to occur for it to play a role alongside the more mature SiC and GaN power device technologies? The low thermal conductivity might be mitigated by transferring devices to another substrate or thinning down the substrate and using a heatsink as well as top-side heat extraction. We give a perspective on the materials’ properties and physics of transport, thermal conduction, doping capabilities, and device design that summarizes the current limitations and future areas of development. A key requirement is continued interest from military electronics development agencies. The history of the power electronics device field has shown that new technologies appear roughly every 10-12 years, with a cycle of performance evolution and optimization. The older technologies, however, survive long into the marketplace, for various reasons. Ga2O3 may supplement SiC and GaN, but is not expected to replace them.
关键词： MOSFETs,β-Ga2O3,rectifiers,power electronics,thermal conductivity,Gallium oxide,Ga2O3,doping,wide bandgap semiconductors,military electronics
更新于2025-09-16 10:30:52