- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Sub-stochiometric MoO <sub/>3</sub> for intermediate band solar cells
摘要： This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm. This structure is suitable for ?xed size processor that only reuse the core and does not require to modulate the core size when m modi?ed. This structure is extracted by applying a nonlinear methodology that gives the designer more ?exibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported ef?cient designs show that the proposed scalable structure achieves a signi?cant reduction in the area ranging from 83.0% to 88.3% and also achieves a signi?cant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identi?cation (RFID) devices.
关键词： Scalable systolic arrays,?nite ?eld inversion,ultra-low power devices,hardware security,ASIC
更新于2025-09-23 15:19:57
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Empty Substrate Integrated Waveguide Fed Patch Antenna Array for 5G mm-Wave Communication Systems
摘要： This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm. This structure is suitable for ?xed size processor that only reuse the core and does not require to modulate the core size when m modi?ed. This structure is extracted by applying a nonlinear methodology that gives the designer more ?exibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported ef?cient designs show that the proposed scalable structure achieves a signi?cant reduction in the area ranging from 83.0% to 88.3% and also achieves a signi?cant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identi?cation (RFID) devices.
关键词： ?nite ?eld inversion,Scalable systolic arrays,ASIC,ultra-low power devices,hardware security
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Sozopol, Bulgaria (2019.9.6-2019.9.8)] 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Machining Error Influnce on Stress State of Conical Thread Joint Details
摘要： This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm. This structure is suitable for ?xed size processor that only reuse the core and does not require to modulate the core size when m modi?ed. This structure is extracted by applying a nonlinear methodology that gives the designer more ?exibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported ef?cient designs show that the proposed scalable structure achieves a signi?cant reduction in the area ranging from 83.0% to 88.3% and also achieves a signi?cant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identi?cation (RFID) devices.
关键词： ?nite ?eld inversion,Scalable systolic arrays,ASIC,ultra-low power devices,hardware security
更新于2025-09-19 17:13:59