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[IEEE 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Qingdao (2018.10.31-2018.11.3)] 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Orientation controlled GaSb nanowires: from growth to application
摘要： In recent years, high-mobility GaSb nanowires have received tremendous attention for high-performance p-type transistors; however, due to the difficulty in achieving thin, uniform and orientation-controlled nanowires (NWs), there is limited report until now addressing their orientation-dependent properties in this important one-dimensional material system, where all these are essential information for the deployment of applications. Using various GaSb NWs CMOS-compatible Pd catalysts, we demonstrated the formation of high-mobility (cid:1766)111(cid:1767)-oriented GaSb nanowires (NWs) via vapor-solid-solid (VSS) growth by the newly developed surfactant-assisted chemical vapor deposition through a complementary experimental and theoretical approach. In contrast to NWs formed by the conventional vapor-liquid-solid (VLS) mechanism, cylindrical-shaped Pd5Ga4 catalytic seeds were present in solid catalysts, our Pd-catalyzed VSS-NWs. As stoichiometric Pd5Ga4 was found to have the lowest crystal surface energy and thus giving rise to a minimal surface diffusion as well as an optimal in-plane interface interface for efficient orientation at epitaxial NW nucleation. Over 95% high crystalline quality NWs were grown in (cid:1766)111(cid:1767) orientation for a wide diameter range of between 10 and 70 nm. Back-gated the field-effect Pd-catalyzed GaSb NWs exhibit a superior peak hole mobility of ～330 cm2 V-1 s-1, close to the mobility limit for a NW channel diameter of ～30 nm with a free carrier concentration of ～1018 cm-3. This suggests that the NWs have excellent homogeneity in phase purity, growth orientation, electrical characteristics. Contact printing process was also used to fabricate large-scale assembly of Pd-catalyzed GaSb NW parallel arrays, confirming the potential constructions and applications of these high-performance electronic devices.
关键词： vapor-solid-solid growth,GaSb nanowires,high-mobility,CMOS-compatible,orientation-controlled
更新于2025-09-11 14:15:04
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[Springer Theses] CMOS-Compatible Key Engineering Devices for High-Speed Silicon-Based Optical Interconnections || CMOS-Compatible Efficient Fiber-to-Chip Coupling
摘要： In this chapter, we study the fiber-to-chip coupling problem in silicon-based optical interconnections. It mainly includes: 1. We have designed and demonstrated a series of fully CMOS-compatible single-tip inverse tapers for edge coupling. We use the SiO2 gap and deep etching method between the taper tip and the edge of the chip to process the high-quality taper tip, and study the effect of the design parameters on the coupling efficiency. We found that the device length has a obvious effect on the device coupling loss, mainly due to the large waveguide propagation loss. Finally, for a inverse taper with a taper tip width of 0.16 μm and a length of 40 μm, the coupling loss of TE and TM at the wavelength of 1550 nm are 1.13 dB/facet and 1.81 dB/facet respectively. The ?1 dB bandwidth is larger than 180 nm. 2. We designed and demonstrated an ultra-compact polarization-insensitive optical combiner. The working principle is based on the two-mode interference. The length of the device is only 5.1 μm, and the excess loss of the two polarizations is both less than 0.1 dB. 3. We designed and demonstrated a novel double-tip inverse taper which consists of two inverse tapers and an ultra-compact polarization-insensitive optical combiner. We have studied the effect of design parameters on coupling loss. And a edge coupler with only 40 μm length is proved. When the wavelength is 1550 nm, the coupling loss for TE and TM are 1.10 dB/facet and 1.52 dB/facet respectively, and the ?1 dB bandwidth is more than 160 nm. Its processing is completely CMOS compatible, and it can be further optimized by the previous multi-layer, multi-stage and cantilever technology.
关键词： double-tip inverse taper,polarization-insensitive optical combiner,fiber-to-chip coupling,inverse tapers,CMOS-compatible,silicon-based optical interconnections,two-mode interference
更新于2025-09-10 09:29:36
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[Springer Theses] CMOS-Compatible Key Engineering Devices for High-Speed Silicon-Based Optical Interconnections || Summary and Future Work
摘要： This dissertation mainly focuses on four important scientific problems in silicon photonics, i.e., silicon electro-optic modulator, advanced multiplexing mechanism, polarization controlling and fiber-to-chip coupling. It systematically puts forward the design theory of silicon electro-optic modulator, investigates advanced multiplexing mechanisms, studies polarization-controlling devices, and explores fiber-to-chip coupling techniques. The research demonstrates high-performance devices fabricated with commercial 130 nm CMOS process, including a high-speed carrier-depletion silicon electro-optic modulator, WDM devices, PDM devices, MDM devices, and ultra-compact polarization splitter-rotators. The work aims to contribute to the field of silicon photonics by providing CMOS-compatible solutions for high-speed silicon-based optical interconnections.
关键词： multiplexing mechanism,CMOS-compatible,fiber-to-chip coupling,polarization controlling,electro-optic modulator,silicon photonics
更新于2025-09-10 09:29:36
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Synchronous 2D/3D Switching System for Service-Compatible 3DTV Broadcasting
摘要： This paper proposes a new broadcasting system for the service-compatible 3DTV in which the 3D service can coexist with the conventional digital TV broadcast. In the proposed system, the commercial 3DTV service can be implemented via the existing DTV channel without utilizing the dedicated 3DTV system. This 2D/3D system interworks with the conventional system and can switch to 2D or 3D service according to the broadcast programming and schedule. The system also provides a mechanism that can prevent the synchronization mismatch between left and right video streams and between the stream and the associated signaling in the 2D/3D transition periods. The picture quality measurements are carried out based on the ITU-R recommended test to check the level of quality of service provided by the proposed scheme. The conformity tests are also performed with the conventional channel and the receiver for the DTV system to confirm the feasibility of the proposed one for the commercial service.
关键词： 3DTV,video quality,service-compatible,3D multiplexer,2D/3D switch
更新于2025-09-10 09:29:36
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Epitaxial Bonding and Transfer Processes for Large-Scale Heterogeneously Integrated Electronic-Photonic Circuitry
摘要： A process ?ow for the heterogeneous integration of III-V epitaxial material onto a silicon host wafer using CMOS-compatible materials and methods toward the goal of forming electronic-photonic circuitry is presented. Epitaxial structures for compound-semiconductor-based transistors are assembled on a silicon carrier wafer using a commercially-available polymer and then formed into distinct patterns for scalable processing. A CMOS-compatible metallization process is performed on the back side collector terminal of the aligned epitaxial structures, followed by a metal-eutectic bonding process that transfers the wafer-scale array of III-V material onto a separate silicon host wafer allowing the fabrication of both electronic and photonic devices on a single wafer. Characterization of the epitaxial bonding and transfer is performed to ensure material alignment is maintained without additional tooling and that the interconnect layer established between III-V collector and silicon host wafer performs as an ohmic contact, thermal path, and mechanical bond compatible with back-end-of-line (BEOL) integrated circuit processing. These processes are shown for GaAs-based light-emitting transistor (LET) epitaxial material to demonstrate that subsequent photonic devices and systems may be patterned into the integrated material allowing a direct electrical interconnect to embedded CMOS-based electronic systems for new functionalities as electronic-photonic integrated circuitry.
关键词： epitaxial bonding,silicon host wafer,metal-eutectic bonding,III-V epitaxial material,electronic-photonic circuitry,heterogeneous integration,CMOS-compatible
更新于2025-09-09 09:28:46
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Hypersonic Surface Phononic Bandgap Demonstration in a CMOS-Compatible Pillar-Based Piezoelectric Structure on Silicon
摘要： We demonstrate a new phononic crystal (PnC) platform with wideband hypersonic phononic bandgaps (PnBGs) for surface acoustic waves (SAWs). These SAW PnCs are fabricated on a CMOS-compatible substrate and constructed by a two-dimensional periodic array of piezoelectric aluminium nitride pillars on silicon to achieve a low-loss all-dielectric PnC platform. Our experimental PnBG results acquired with integrated wideband SAW ?lters (i.e., two slanted interdigital transducers as an emitter and a receiver) show a surface PnBG from 1.6 to 1.75 GHz for the fabricated surface PnC, enabling the formation of low-loss hypersonic PnC-based devices for a wide range of ultrahigh-frequency applications, including wireless communications.
关键词： CMOS-compatible,phononic crystal,piezoelectric,hypersonic,surface acoustic waves
更新于2025-09-09 09:28:46
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[IEEE 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Qingdao, China (2018.10.31-2018.11.3)] 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Non-filamentary Pd/Al<inf>2</inf>O<inf>3</inf>/TaO<inf>x</inf>/Ta Memristor as Artificial Synapse for Neuromorphic Computing
摘要： We report a fully CMOS compatible bilayer, forming-free and non-filamentary memristive device with excellent bidirectional analog switching behavior as artificial synapse for neuromorphic computing applications. The bilayer stack structure, consisting of 8 nm TaOx formed via oxidation process on Ta bottom electrode and 7 nm Al2O3 via atom layer deposition (ALD), is sandwiched between the Ta bottom electrode and Pd top electrode. The Pd/Al2O3/TaOx/Ta device shows bidirectional analog resistive switching behaviors, and multilevel conductance states (>60) with satisfying retention time can be obtained. Long term plasticity, consisting of long-term potentiation (LTP) and long-term depression (LTD), have been demonstrated based our device. And a nearly linear conductance change behavior is obtained by optimizing the training scheme: adopting non-identical training pulses. A two-layer perceptron neural network was performed to estimate the synapse characteristics of our devices. More than 94% recognition accuracy of MNIST handwritten digit dataset are achieved. Based on these results, the device is a promising emulator for biology synapse, and has a great potential to be used in neuromorphic systems.
关键词： memristor,neuromorphic computing,analog switching,artificial synapse,CMOS compatible
更新于2025-09-09 09:28:46