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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Quantum Rangefindng
摘要： Transformer parasitics such as leakage inductance and self-capacitance are rarely calculated in advance during the design phase, because of the complexity and huge analytical error margins caused by practical winding implementation issues. Thus, choosing one transformer architecture over another for a given design is usually based on experience or a trial and error approach. This paper presents analytical expressions for calculating leakage inductance, self-capacitance, and ac resistance in transformer winding architectures (TWAs), ranging from the common noninterleaved primary/secondary winding architecture, to an interleaved, sectionalized, and bank winded architecture. The calculated results are evaluated experimentally, and through finite-element simulations, for an RM8 transformer with a turns ratio of 10. The four TWAs such as, noninterleaved and nonsectioned, noninterleaved and sectioned, interleaved and nonsectioned, and interleaved and sectioned, for an EF25 transformer with a turns ratio of 20, are investigated and practically implemented. The best TWA for an RM8 transformer in a high-voltage bidirectional flyback converter, used to drive an electro active polymer based incremental actuator, is identified based on the losses caused by the transformer parasitics. For an EF25 transformer, the best TWA is chosen according to whether electromagnetic interference due to the transformer interwinding capacitance, is a major problem or not.
关键词： energy efficiency,switch-mode power converters,transformer winding architectures,Actuator,high-voltage dc–dc converters,high-voltage transformer,transformer parasitics
更新于2025-09-19 17:13:59
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[IEEE 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018) - Paris, France (2018.7.8-2018.7.13)] 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018) - High Voltage CT Ratio Errors Dependency on Voltage and Power Factor of the Metered Load
摘要： This paper describes the results of the performance evaluation of the ratio errors of a high-voltage current transformer (CT) and a high-voltage combined current and voltage transformer (CTVT) under different operating conditions. The ratio errors of the CT and CTVT are measured at different power factors of the primary and secondary windings in which the CT (or part of the CTVT) is operated at high voltages. The results show that the ratio error of the CT is significantly different at different power factors, and the effects of the power factor on the ratio error of the CTVT are also significant. The measurement results are compared with the theoretical calculations, and the differences between them are discussed.
关键词： ratio errors,Current transformer,voltage transformer,load
更新于2025-09-10 09:29:36
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[IEEE 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018) - Paris, France (2018.7.8-2018.7.13)] 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018) - A Sampling-Based Ratio Bridge for Calibrating Voltage Transformers
摘要： This paper describes the setup of a sampling-based ratio bridge for calibrating voltage transformers. The advantage of this ratio method is that voltage transformers with different transformer ratios can be easily compared. Initial measurements of the components of the bridge indicate low systematic errors, negligible voltage dependency and low phase errors around 50 / 60 Hz. This indicates an attainable uncertainty of below 2 ppm for the ratio error and 0.5 μrad for the phase displacement of voltage transformers.
关键词： Voltage transformer,sampling,high voltage,uncertainty,precision measurements
更新于2025-09-10 09:29:36
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99 % Efficient 10 kV SiC-Based 7 kV/400 V DC-Transformer for Future Data Centers
摘要： The power supply chain of data centers from the medium voltage (MV) utility grid down to the chip level voltage consists of many series connected power conversion stages and accordingly shows a relatively low ef?ciency. Solid-State Transformers (SSTs) could improve the ef?ciency by substantially reducing the number of power conversion stages and/or directly interfacing the MV AC grid to a 400 V DC bus, from where tens of server racks with a power consumption of several kilowatts could be supplied by individual SSTs. The recent development of SiC MOSFETs with a blocking voltage of 10 kV enables the realization of a simple and hence highly reliable two-stage SST topology, consisting of an AC/DC PFC recti?er and a subsequent isolated DC/DC converter. In this context, an isolated 25 kW, 48 kHz, 7 kV to 400 V series resonant DC/DC converter based on 10 kV SiC MOSFETs is realized and tested in this paper. To achieve zero voltage switching (ZVS) of all MOSFETs, a special modulation scheme to actively control the amount of the switched magnetizing current on the MV and LV side is implemented. Furthermore, the design of all main components and especially the electrical insulation of the employed medium frequency (MF) transformer is discussed in detail. Calorimetric ef?ciency measurements show that a full-load ef?ciency of 99.0 % is achieved, while the power density reaches 3.8 kW/L (63 W/in3).
关键词： ZVS,isolated DC/DC,medium-voltage transformer,10kV SiC MOSFETs,soft-switching,Medium-voltage,calorimetric measurement
更新于2025-09-04 15:30:14