[IEEE 48th European Solid-State Device Research Conference (ESSDERC 2018) - Dresden (2018.9.3-2018.9.6)] 2018 48th European Solid-State Device Research Conference (ESSDERC) - Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic

摘要： We propose implementation of a 1-bit full adder following Capacitive Adiabatic Logic (CAL) paradigm. Combinational logic functions including AND, OR, and XOR gates are realized by five-terminal comb-drive MEMS elements. By in CAL, we demonstrate the ability of MEMS device to be cascadable. By MEMS compact modeling, we can evaluate the energy dissipation and speed of adding operation. In the presented full adder, 99.6% of the energy transferred to the device is recovered for later use when it operates on 2 kOPS.