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[IEEE 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE) - Aswan City, Egypt (2019.10.23-2019.10.25)] 2019 IEEE Conference on Power Electronics and Renewable Energy (CPERE) - Common-Mode Voltage Analysis of Three-phase Quasi-Z Source Inverters for Transformerless Photovoltaic Systems
摘要： Reducing the capacitance of programmable capacitor arrays (PCAs), commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data are available for small capacitors. We report mismatch measurement for a 2-fF poly–insulator–poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors’ knowledge. Instead of using complicated custom on-chip circuitry, direct mismatch measurement is demonstrated and veri?ed using Monte Carlo simulations and experimental measurements. Capacitive test structures composed of 9-bit PCAs are implemented in a low-cost 0.35-μm CMOS process. Measured data are compared to the mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2-fF unit capacitor, which is better than the reported mismatch of metal–oxide–metal (MOM) fringing capacitors implemented in an advanced 32-nm CMOS process.
关键词： programmable capacitor array (PCA),Analog-to-digital converter (ADC),energy-ef?cient circuits,mismatch characterization,capacitance-to-digital converter (CDC),capacitor mismatch
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE 2nd International Conference on Renewable Energy and Power Engineering (REPE) - Toronto, ON, Canada (2019.11.2-2019.11.4)] 2019 IEEE 2nd International Conference on Renewable Energy and Power Engineering (REPE) - The Potential and analysis of Grid-connected Photovoltaic System in residential houses in Libya : Near-term solution of electricity shortage: A case study in Tripoli
摘要： Reducing the capacitance of programmable capacitor arrays (PCAs), commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data are available for small capacitors. We report mismatch measurement for a 2-fF poly–insulator–poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors’ knowledge. Instead of using complicated custom on-chip circuitry, direct mismatch measurement is demonstrated and veri?ed using Monte Carlo simulations and experimental measurements. Capacitive test structures composed of 9-bit PCAs are implemented in a low-cost 0.35-μm CMOS process. Measured data are compared to the mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2-fF unit capacitor, which is better than the reported mismatch of metal–oxide–metal (MOM) fringing capacitors implemented in an advanced 32-nm CMOS process.
关键词： programmable capacitor array (PCA),Analog-to-digital converter (ADC),energy-ef?cient circuits,mismatch characterization,capacitance-to-digital converter (CDC),capacitor mismatch
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE SENSORS - Montreal, QC, Canada (2019.10.27-2019.10.30)] 2019 IEEE SENSORS - AC/DC Millivoltage Sensor by means of ITO-coated Optical Fibers: Towards Monitoring of Biosignals
摘要： Reducing the capacitance of programmable capacitor arrays (PCAs), commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data are available for small capacitors. We report mismatch measurement for a 2-fF poly–insulator–poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors’ knowledge. Instead of using complicated custom on-chip circuitry, direct mismatch measurement is demonstrated and veri?ed using Monte Carlo simulations and experimental measurements. Capacitive test structures composed of 9-bit PCAs are implemented in a low-cost 0.35-μm CMOS process. Measured data are compared to the mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2-fF unit capacitor, which is better than the reported mismatch of metal–oxide–metal (MOM) fringing capacitors implemented in an advanced 32-nm CMOS process.
关键词： programmable capacitor array (PCA),capacitor mismatch,mismatch characterization,energy-ef?cient circuits,Analog-to-digital converter (ADC),capacitance-to-digital converter (CDC)
更新于2025-09-23 15:19:57
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Electric field-induced linear electro-optic effect observed in silicon-organic hybrid ring resonator
摘要： Reducing the capacitance of programmable capacitor arrays (PCAs), commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data are available for small capacitors. We report mismatch measurement for a 2-fF poly–insulator–poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors’ knowledge. Instead of using complicated custom on-chip circuitry, direct mismatch measurement is demonstrated and veri?ed using Monte Carlo simulations and experimental measurements. Capacitive test structures composed of 9-bit PCAs are implemented in a low-cost 0.35-μm CMOS process. Measured data are compared to the mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2-fF unit capacitor, which is better than the reported mismatch of metal–oxide–metal (MOM) fringing capacitors implemented in an advanced 32-nm CMOS process.
关键词： programmable capacitor array (PCA),Analog-to-digital converter (ADC),energy-ef?cient circuits,mismatch characterization,capacitance-to-digital converter (CDC),capacitor mismatch
更新于2025-09-23 15:19:57